This thesis introduces the ‘tunable’ piezoelectric transformers (TPT) which provide an extra control terminal, used in this case, to regulate the output voltage. A detailed mathematical analysis is done on the electrical equivalent circuit of the TPT to understand the effect of control terminal loading on the circuit performance. Based on this analysis, a variable capacitor connected across the control terminal is proposed to regulate the output voltage for line and load variations is suggested. The concept of ‘tunability’ in a TPT is introduced and mathematical conditions are derived to achieve the required ‘tunability’. This analysis can help a TPT designer to design the TPT for a specific application and predict the load and line regulations limits for a given design. A circuit implementation of the variable capacitor, intended for control, is presented. With the proposed control circuit design, the effective value of a fixe capacitor can be controlled by controlling the duty cycle of a switch. Hence, this enables pulse width modulated (PWM) control for the TPT based converter operating at a constant frequency. Fixed frequency operation enables a high efficiency operation of TPT near its resonant frequency and the complete secondary control requires no isolation in the voltage feedback and control circuit. This prevents any ‘cross-talk’ between primary and secondary terminals and reduces the component count. The design of series input inductor for achieving zero voltage switching (ZVS) in the inverter switches for the new control is also discussed. Experimental results for two different TPT designs are presented. Their differences in structure and its effect on the circuit performance has been discussed to support the mathematical analysis. / Master of Science

Piezoelectric ceramics are characterized as smart materials and have been widely used in the area of actuators and sensors. The principle operation of a piezoelectric transformer (PT) is a combined function of actuators and sensors so that energy can be transformed from electrical form to electrical form via mechanical vibration. Since PTs behave as band-pass filters, it is particularly important to control their gains as transformers and to operate them efficiently as power-transferring components. In order to incorporate a PT into amplifier design and to match it to the linear or nonlinear loads, suitable electrical equivalent circuits are required for the frequency range of interest. The study of the accuracy of PT models is carried out and verified from several points of view, including input impedance, voltage gain, and efficiency. From the characteristics of the PTs, it follows that the efficiency of the PTs is a strong function of load and frequency. Because of the big intrinsic capacitors, adding inductive loads to the PTs is essential to obtain a satisfactory efficiency for the PTs and amplifiers. Power-flow method is studied and modified to obtain the maximum efficiency of the converter. The algorithm for designing a PT converter or inverter is to calculate the optimal load termination, YOPT, of the PT first so that the efficiency (power gain) of the PT is maximized. And then the efficiency of the dc/ac inverter is optimized according to the input impedance, ZIN, of the PT with an optimal load termination. Because the PTs are low-power devices, the general requirements for the applications of the PTs include low-power, low cost, and high efficiency. It is important to reduce the number of inductive components and switches in amplifier or dc/ac inverter designs for PT applications. High-voltage piezoelectric transformers have been adopted by power electronic engineers and researchers worldwide. A complete inverter with HVPT for CCFL or neon lamps was built, and the experimental results are presented. However, design issues such as packaging, thermal effects, amplifier circuits, control methods, and matching between amplifiers and loads need to be explored further. / Ph. D.

In this thesis, coupled inductors have been applied to multiphase DC-DC converters. Detailed analysis has been done to investigate the benefits of directly coupled inductors and inversely coupled inductors, compared to conventional uncoupled inductors. In general, coupled inductors for multiphase DC-DC converters have inherent benefits such as excellent current sharing characteristics, immunity to component tolerance and reduction in current control complexity. Specifically, by employing directly coupled inductors for multiphase DC-DC converters, overall current ripple can be effectively reduced, compared to that of uncoupled inductors. For inversely coupled inductors, phase current ripple can be reduced if operating points and coupling coefficients are carefully chosen. As for small-signal characteristics, inversely coupled inductors have the advantages of broadening the bandwidth of multiphase DC-DC converters and being more immune to load variation at low frequencies. On the other hand, directly coupled inductors have the benefit of low sensitivity to input variation at high frequencies. In addition, the proposed new structure for multiphase DC-DC converters has excellent current sharing performance and reduced current ripple. Computer simulations have been done and hardware prototypes have been built to validate the concepts.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Current trends in electronics are toward the use of reduced voltages. In the past, 5 V and higher voltages have been the standard, however, currently, 3.3V and 2.5V circuits are becoming increasingly common. While the operating voltage is decreasing, electronic systems are becoming more complex. The net result is that in many, cases, the current required by the next generation of electronics will be far greater than in the past. These increased currents and low voltages pose dramatic problems for designers not the least of which is the effect of electronic packaging and circuit implementation on the overall power supply performance. In addition, for many applications, space and weight are at a premium and converters are needed to power low voltage circuit assemblies that are highly efficient, low in weight, and small in total height and foot print. This dissertation addresses these trends and needs through the design, fabrication and evaluation of a 3.3V DC/DC converter. Designs of 3.3V, 2.5V, and 1.5V are presented and evaluated while a 3.3V, 100 watt converter with a power density of 157 watts/in³ has been fabricated and evaluated in a miniature form. This converter utilizes a implementation strategy developed by the author which was selected due to its ability to handle the current levels required and its compact size. Specific contributions of this work include: • Analysis of the effects of packaging on low voltage high current converters in order to provide a guideline for converter implementation. This analysis has been performed for 3.3 V, 2.5 V, and 1.5 V designs, respectively. • Development of high efficiency 2.5 V, 100 watt and 1.5 V, 75 watt designs based on previously reported half bridge topologies. • Development of a packaging strategy which allows the fabrication of low voltage compact converters with high efficiency. A 3.3 V converter has been fabricated and with the simulated data validated these experimental results. For very low (less than 50 watts and / or less than 10 amps) and high power levels (hundreds of amps or kilowatts), the implementation strategy is normally clear; PCB/IMS, and DBC respectively. However, for applications in the middle range of power or current level, the optimum implementation is often unclear. The question that this work seeks to answer is under what conditions are different implementation schemes most suitable. / Ph. D.

To support the increasingly demanding requirements for power conversion units, a digitally controlled dual output stage buck converter is designed. The system consists of a dual output stage, which includes an auxiliary buck output stage connected in parallel with a main output stage. The auxiliary output stage is only active during load transient to suppress the output voltage variation. A digital controller is designed to control both stages with a linear/nonlinear control scheme. Nonlinear control is applied during load transient based on the capacitor charge balance principle; whereas linear PID control governs the steady state operation. The design is verified with simulation and experimentally with discrete components. The controller is realized with a FPGA with preset output stage parameters. The experimental result shows a 60% reduction of output voltage variation for a heavy-to-light load transient.

To support the increasingly demanding requirements for power conversion units, a digitally controlled dual output stage buck converter is designed. The system consists of a dual output stage, which includes an auxiliary buck output stage connected in parallel with a main output stage. The auxiliary output stage is only active during load transient to suppress the output voltage variation. A digital controller is designed to control both stages with a linear/nonlinear control scheme. Nonlinear control is applied during load transient based on the capacitor charge balance principle; whereas linear PID control governs the steady state operation. The design is verified with simulation and experimentally with discrete components. The controller is realized with a FPGA with preset output stage parameters. The experimental result shows a 60% reduction of output voltage variation for a heavy-to-light load transient.

This thesis is an ongoing project of Ericsson with collaboration of Blekinge Institute of Technology [BTH], and Linneaus University [LNU] to compare the functionality and performance of three controllers Polynomial Pole Placement, PID [Proportional Integral Derivative] and PD controller in third order. This paper presents the state space modeling approach of DC-DC Buck converter. The main aim of this thesis is, by considering the buck converter system of Ericsson BMR450 with the PID, POLYNOMIAL and PD controllers at feedback loop, thus running their Matlab file with their appropiate Simulink block diagram, and comparing the three controllers performance by verifying their appropiate output graphs. The third order controller design is complicated and response is slow. The second order design is easy and gives better responses than third order Polynomial, PID and PD controllers. / As per the results point of view, the polynomial performed well than PID and PD controllers. The simulations show that the polynomial controller reaches the reference voltage very well, were the PID and PD result does not differ very much while meeting with the required reference voltage. Thus we conclude that the Polynomial controller design and results were better than the PID and PD Controllers. If we compare both the second order [4] and third order controller methods, The second order controllers are easy in design and gives better responses than third order polynomial PID and PD controllers. / ERCS.MADHU KIRAN, D.NO: 1/1/131, B.C.COLONY, MUTHUKUR, NELLORE, ANDHRA PRADESH, INDIA. PIN - 524344. THOTA. Partha Saradhi, C/O CH SUVARNA RAJU D.NO: 4-5-47, VEGIVARI CHAVADI, KOTHA PETA, WARD NO:21, KOVVUR, WEST GODAVARI,ANDHRA PRADESH, INDIA PIN - 534350,