Doctor of Philosophy / Department of Electrical and Computer Engineering / Behrooz Mirafzal / Corrective schemes for facilitating continued operation of dc-ac converters during internal and external abnormalities are presented in this dissertation. While some of the developed techniques are suited for any dc-ac converter topology, most of the presented methodologies are designed specifically for cascaded H-bridge (CHB) multilevel converters. While CHB provide increased scalability and efficiency compared to traditional topologies, these converters are more likely to experience internal faults due to the additional components required. Realizing the full potential of CHB converters requires fault tolerant techniques, such as those demonstrated in this dissertation. Adaptive sinusoidal pulse width modulation (ASPWM) is introduced in this dissertation as a method which enables CHB to directly utilize time-variant dc sources, increasing CHB flexibility when compared to traditional pulse width modulation (PWM) methods which require dc sources with equal magnitudes or with magnitudes existing in specific ratios. Two alternative algorithms are presented to enable ASPWM implementation, providing a trade off between system performance and required sensor circuitry. This dissertation also introduces a load independent analytical approach for identifying discordant operating points, i.e. operating points where some cells in an asymmetric CHB leg regenerate power while the overall leg delivers power, or vice-versa. Identification of these points is essential due to the deleterious effects which can result from extended discordant operation, for instance overcharging of batteries leading to lifespan degradation or even catastrophic failures such as fires or explosions. Additionally, a method for rapidly identifying, isolating, and verifying internal IGBT open-circuit and gate-driver faults is presented in this dissertation to address the increased probability of switch failures occurring within CHB. The proposed approach enables converter operation to continue in the event of gate-driver or open-circuit faults, but avoids unnecessary converter reconfiguration due to gate-misfiring faults. For a CHB leg with M cells, the proposed technique identifies and isolates open-circuit switch faults in less than 2M measurement (sampling) cycles, and verification is completed in less than one full fundamental cycle. Furthermore, this dissertation introduces a real-time implementable atypical PWM technique which enables increased dc bus utilization under a wide range of non-ideal operating conditions. While this approach is suitable for a wide range of converters operating under external abnormalities, for instance maximizing dc bus utilization for converters providing auxiliary services such as negative-sequence compensation, this approach also facilitates operation of CHB with faulty cells. The proposed method can be used with any control technique and any carrier-based PWM method, enabling its implementation in both symmetric and asymmetric CHB. In addition to these fault tolerant techniques, a novel approach for analyzing the active- and reactive-power deliverable by grid-interactive converters is proposed. This method facilitates performance comparisons for various converter configurations, simplifying the process for selecting filter components, dc bus voltages, and other system parameters. This analytical approach also enables converter performance to be analyzed during internal and external fault events, allowing assessment of converter robustness. The efficacy of the developed techniques are supported by MATLAB/Simulink simulations as well as experimental data obtained using a laboratory-scale cascaded H-bridge multilevel converter.

Made available in DSpace on 2016-08-17T14:53:28Z (GMT). No. of bitstreams: 1 Dissertacao Felipe Simoes Freitas e Silva.pdf: 5795737 bytes, checksum: dc589a2115d1b568db1a3c2b9de3f80c (MD5) Previous issue date: 2014-04-25 / Conselho Nacional de Desenvolvimento Científico e Tecnológico / This work presents the study, modelling and assembling of a three-phase bidirectional DCAC converter suitable for operating as an interface between an energy storage system based on a battery bank and an isolated microgrid. The converter consists of two stages: a DC-DC stage implemented with a bidirectional half-bridge converter that operates on buck or boost mode (during charge or discharge of the ESS, respectively), and a DC-AC full-bridge three-phase bidirectional inverter. The two stages are connected through a DC link, which also works as a power-decoupling element. Isolation from the microgrid is obtained with a :-Y low frequency transformer. A control strategy is proposed where the DC-DC stage regulates the DC link voltage level while the DC-AC controls the three-phase output voltage and frequency, therefore acting as a grid-forming converter (GFC). A 15kW prototype was successfully built and tested in different situations. Simulation and experimental results are shown. / Esta dissertação apresenta o estudo, modelagem e montagem de um conversor bidirecional CC-CA trifásico de múltiplos estágios, projetado para operar como interface entre um sistema de armazenamento e uma minirrede isolada. O conversor consiste de dois estágios de conversão: um estágio de conversão CC-CC, implementado com um conversor buck-boost de meia ponte, que opera em modo buck ou boost (durante o carga ou descarga do sistema de armazenamento, respectivamente), e um estágio de conversão CC-CA composto por um conversor CC-CA trifásico. Os dois estágios são conectados por um elo CC, que funciona como um elemento de desacoplamento de potência. Isolação galvânica é obtida através de um transformador de baixa frequência. Uma estratégia de controle é utilizada na qual o estágio CC-CC controla a tensão do elo CC enquanto o estágio CC-CA controla a tensão e a frequência da minirrede, atuando, portanto, como um conversor formador de rede (CFR). Um protótipo foi montado e testado em diferentes situações. Resultados de simulação e de testes de bancada são mostrados.

Les convertisseurs statiques triphasés AC/DC/AC à structure tension sont largement utilisés dans de nombreuses applications de puissance. La continuité de service de ces systèmes ainsi que leur sécurité, leur fiabilité et leurs performances sont aujourd'hui des préoccupations majeures de ce domaine lié à l'énergie. En effet, la défaillance du convertisseur peut conduire à la perte totale ou partielle du contrôle des courants de phase et peut donc provoquer de graves dysfonctionnements du système, voire son arrêt complet. Afin d'empêcher la propagation du défaut aux autres composants du système et assurer la continuité de service en toute circonstance lors d'une défaillance du convertisseur, des topologies de convertisseur "fault tolerant" associées à des méthodes efficaces et rapides de détection et de compensation de défaut doivent être mises en oeuvre. Dans ce mémoire, nous étudions la continuité de service de trois topologies de convertisseurs AC/DC/AC avec ou sans redondance, lors de la défaillance d'un de leurs interrupteurs. Deux applications sont ciblées : l'alimentation d'une charge RL triphasée et un système éolien de conversion de l'énergie basé sur une MADA. Un composant FPGA est utilisé pour la détection du défaut, afin de réduire autant que possible son temps de détection. Des variantes permettant d'optimiser la méthode de détection de défaut sont également proposées et évaluées. Les trois topologies de convertisseurs proposées, associées à leurs contrôleurs, ont été validées de la modélisation/ simulation à la validation sur banc de test expérimental, en passant par le prototypage "FPGA in the Loop" du FPGA, destiné plus spécifiquement à la détection du défaut / AC/DC/AC converters are widely being used in a variety of power applications. Continuity of service of these systems as well as their reliability and performances are now of the major concerns. Indeed, the failure of the converter can lead to the total or partial loss of the control of the phase currents and can cause serious system malfunction or shutdown. Thus, uncompensated faults can quickly endanger the system. Therefore, to prevent the spread of the fault to the other system components and to ensure continuity of service, fault tolerant converter topologies associated to quick and effective fault detection and compensation methods must be implemented. In this thesis, we present the continuity of service of three AC/DC/AC fault tolerant converters with or without redundancy, in the presence of a fault in one of their switches. Two types of applications are studied: the supply off a three-phase charge and a wind energy conversion system based on a DFIG. An FPGA based implementation is used for fault detection, in order to reduce the detection time as much as possible. Three optimizations in the fault detection method are also presented. During these researches, the three proposed converter topologies and their controllers are validated in simulations and also experimentally, while being validated in a "FPGA in the Loop" prototyping

High frequency link power converters for DC – 3Φ AC applications are investigated. Low cost, reduced size, galvanic isolation and efficient large boosting of voltage level are the key motivations behind the selection of such topologies. This thesis proposes high frequency link 3Φ inverters for three wire and four wire systems. The proposed topologies have the simplest power circuit configuration and commutation requirements among all high frequency link topologies reported in the literature. A full load efficiency greater than 90% is achieved with a passive snubber. The effect of various circuit non-idealities are common and important for desirable performances of these topologies. A few such issues are highlighted. Firstly, the special commutation requirement of the power circuit causes a non-linear distortion in the output voltages and thus makes the gain of the power converter time varying. A simple compensation technique is adopted to mitigate the problem. Secondly, the high frequency transformer should operate with only switching frequency component. However, in the practical situations a significant amount of low frequency component gets injected into the transformer and results in peaky transformer magnetizing current unless it is over designed. A suitable measure is incorporated in the proposed topologies to achieve a magnetic protection. The power circuit topology is used as stand-by AC power supply. These are of interest for Uninterruptible Power Supply (UPS) and Micro-grid applications. One of the main objectives of such supplies is to provide a high quality and highly reliable power to the connected loads. A voltage regulation loop based on proportional + multiresonant controller is proposed to achieve excellent quality of the output voltage with unbalanced and nonlinear loadings. The factors influencing regulation and stability of the voltage waveform are identified and necessary modifications are carried out to improve the performance. The potential of this voltage regulation loop along with P/Q droop technique and a simple resistive virtual output impedance loop is exploited to achieve decentralized paralleling of inverters. A trade off between the output voltage power quality and the sharing accuracy is examined. The total harmonic distortion and degree of unbalance in the output voltage waveform are experimentally measured well below the specified limit for stand alone AC supplies with an excellent sharing accuracy. Some of the grid interactive modes are addressed for the completeness of the work. A shunt compensator system and a double conversion system based on the same high frequency link converter are experimentally evaluated. These systems can find their application in UPS systems. A few important observations on the power circuit performances are indicated.