- About
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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
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Design of a MMIC serial to parallel converter in Gallium Arsenide. / Konstruktion av en MMIC serie-till-parallellomvandlare på Gallium Arsenid.Nilsson, Tony, Samuelsson, Carl January 2001 (has links)
A 5-bit MMIC serial to parallel converter has been designed in Gallium Arsenide. It is intended to be used together with a 5-bit True Time Delay (TTD) circuit, but it can easily be expanded into an arbitrary number of bits. The circuit has been designed with a logic style called DCFL and a 0.20 mm process (ED02AH) from OMMIC has been used to fabricate the circuit. The chip size of this 5-bit MMIC serial to parallel converter is 2.0x0.8 mm (including pads) and close to two hundred transistors are used. Due to the complexity of the transistor models the complete serial to parallel converter has not been fully simulated. However, the smaller building blocks like inverter, latch, etc. have been simulated successfully. These blocks were assembled into the complete circuit.
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Design of a MMIC serial to parallel converter in Gallium Arsenide. / Konstruktion av en MMIC serie-till-parallellomvandlare på Gallium Arsenid.Nilsson, Tony, Samuelsson, Carl January 2001 (has links)
<p>A 5-bit MMIC serial to parallel converter has been designed in Gallium Arsenide. It is intended to be used together with a 5-bit True Time Delay (TTD) circuit, but it can easily be expanded into an arbitrary number of bits. The circuit has been designed with a logic style called DCFL and a 0.20 mm process (ED02AH) from OMMIC has been used to fabricate the circuit. The chip size of this 5-bit MMIC serial to parallel converter is 2.0x0.8 mm (including pads) and close to two hundred transistors are used. Due to the complexity of the transistor models the complete serial to parallel converter has not been fully simulated. However, the smaller building blocks like inverter, latch, etc. have been simulated successfully. These blocks were assembled into the complete circuit.</p>
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Mapování vyhledávacích tabulek z jazyka P4 do technologie FPGA / Mapping of Match Tables from P4 Language to FPGA TechnologyKekely, Michal January 2016 (has links)
This thesis deals with design and implementation of mapping of match action tables from P4 language to FPGA technology. Goal of the thesis was to describe key principles, which need to be understood in order to design such a mapping and function of algorithms needed, apply these principles by implementing them and analyze the speed and memory requirements of such an implementation. Outcome provides configurable hardware unit capable of classifying packets and connection between the unit and match action tables from P4 language. The implementation is based on DCFL algorithm and requires less memory compared to HiCuts and HyperCuts algorithms while being comparably fast at worst-case scenarios.
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