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The fork-join framework project is one of the more challenging programming assignments in the computer science curriculum at Virginia Tech. Students in Computer Systems must manage a pool of threads to facilitate the shared execution of dynamically created tasks. This project is difficult because students must overcome the challenges of concurrent programming and conform to the project's specific semantic requirements. When working on the project, many students received inconsistent test results and were left confused when debugging. The suggested debugging tool, Helgrind, is a general-purpose thread error detector. It is limited in its ability to help fix bugs because it lacks knowledge of the specific semantic requirements of the fork-join framework. Thus, there is a need for a special-purpose tool tailored for this project. We implemented Willgrind, a debugging tool that checks the behavior of fork-join frameworks implemented by students through dynamic program analysis. Using the Valgrind framework for instrumentation, checking statements are inserted into the code to detect deadlock, ordering violations, and semantic violations at run-time. Additionally, we extended Willgrind with happens-before based checking in WillgrindPlus. This tool checks for ordering violations that do not manifest themselves in a given execution but could in others. In a user study, we provided the tools to 85 students in the Spring 2017 semester and collected over 2,000 submissions. The results indicate that the tools are effective at identifying bugs and useful for fixing bugs. This research makes multithreaded programming easier for students and demonstrates that special-purpose debugging tools can be beneficial in computer science education. / Master of Science

Early closure to functional correctness of the final chip has become a crucial success factor in the semiconductor industry. In this context, the tedious task of functional debugging poses a significant bottleneck in modern electronic design processes, where new problems related to debugging are constantly introduced and predominantly performed manually. This dissertation proposes methodologies that address two emerging debugging problems in modern design flows. First, it proposes a novel and automated triage framework for Register-Transfer-Level (RTL) debugging. The proposed framework employs clustering techniques to automate the grouping of a plethora of failures that occur during regression verification. Experiments demonstrate accuracy improvements of up to 40% compared to existing triage methodologies. Next, it introduces new techniques for Field Programmable Gate Array (FPGA) debugging that leverage reconfigurability to allow debugging to operate without iterative executions of computationally-intensive design re-synthesis tools. Experiments demonstrate productivity improvements of up to 30 x vs. conventional approaches.

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Abstract not available

Zugl.: Berleey, Univ. of California, Diss., 2005 / Lizenzpflichtig

This thesis presents the results of two studies that investigate the question of what interruption-styles are most appropriate for end-user programmers who are debugging programs. In the studies, end-user programmers are presented with surprises that encourage them to investigate, use, and learn about debugging devices in their programming environment. We used various interruption-styles to present these surprises to the end-user programmers, and we evaluated how they affected the end-user programmers ability to learn about the debugging features, their accuracy at debugging their programs, and how accurate they were at judging how well they had debugged their programs. The three styles we compared were immediate-style interruptions (which force the user to acknowledge them), low-intensity negotiated-style interruptions (which do not force the user to acknowledge them, but rather use visual elements such as red circles around cell values in order to notify users that there is something for them to do), and high-intensity negotiated-style interruptions (which are the same as low-intensity negotiated-style interruptions except that the visual elements are more intense, e.g. they are larger and they blink). We found that low-intensity negotiated-style interruptions best supported end-user programmers debugging, learning, and self-assessment. We also found that immediate-style and high-intensity negotiated-style interruptions had very similar effects on the end-user programmers. / Graduation date: 2004

This paper presents an approach to compiler correctness in which the compiler generates a proof that the transformed program correctly implements the input program. A simple proof checker can then verify that the program was compiled correctly. We call a compiler that produces such proofs a credible compiler, because it produces verifiable evidence that it is operating correctly. / Singapore-MIT Alliance (SMA)

With the growing complexity of modern VLSI designs, design errors become increasingly common. Design debugging today emerges as a bottleneck in the design flow, consuming up to 30% of the overall design effort. Unfortunately, design debugging is still a predominantly manual process in the industry. To tackle this problem, we enhance existing automated debugging tools and extend their applications to different design domains. The first contribution improves the performance of automated design debugging tools by using structural circuit properties, namely dominance relationships and non-solution implications. Overall, a 42% average reduction in solving run-time demonstrates the efficacy of this approach. The second contribution presents an automated debugging methodology for clock-gating design. Using clock-gating properties, we optimize existing debugging techniques to localizes and rectifies the design errors introduced by clock-gating implementations. Experiments show a 6% average reduction in debugging time and 80% of the power-savings retained.

With the growing complexity of modern VLSI designs, design errors become increasingly common. Design debugging today emerges as a bottleneck in the design flow, consuming up to 30% of the overall design effort. Unfortunately, design debugging is still a predominantly manual process in the industry. To tackle this problem, we enhance existing automated debugging tools and extend their applications to different design domains. The first contribution improves the performance of automated design debugging tools by using structural circuit properties, namely dominance relationships and non-solution implications. Overall, a 42% average reduction in solving run-time demonstrates the efficacy of this approach. The second contribution presents an automated debugging methodology for clock-gating design. Using clock-gating properties, we optimize existing debugging techniques to localizes and rectifies the design errors introduced by clock-gating implementations. Experiments show a 6% average reduction in debugging time and 80% of the power-savings retained.