The automatic generation of instruction set extensions to provide application-specific acceleration for embedded processors has been a productive area of research in recent years. There have been incremental improvements in the quality of the algorithms that discover and select which instructions to add to a processor. The use of automatic algorithms, however, result in instructions which are radically different from those found in conventional, human-designed, RISC or CISC ISAs. This has resulted in a gap between the hardware’s capabilities and the compiler’s ability to exploit them. This thesis proposes and investigates the use of a high-level compiler pass that uses graph-subgraph isomorphism checking to exploit these complex instructions. Operating in a separate pass permits techniques to be applied that are uniquely suited for mapping complex instructions, but unsuitable for conventional instruction selection. The existing, mature, compiler back-end can then handle the remainder of the compilation. With this method, the high-level pass was able to use 1965 different automatically produced instructions to obtain an initial average speed-up of 1.11x over 179 benchmarks evaluated on a hardware-verified cycle-accurate simulator. This result was improved following an investigation of how the produced instructions were being used by the compiler. It was established that the models the automatic tools were using to develop instructions did not take account of how well the compiler could realistically use them. Adding additional parameters to the search heuristic to account for compiler issues increased the speed-up from 1.11x to 1.24x. An alternative approach using a re-designed hardware interface was also investigated and this achieved a speed-up of 1.26x while reducing hardware and compiler complexity. A complementary, high-level, method of exploiting dual memory banks was created to increase memory bandwidth to accommodate the increased data-processing bandwidth provided by extension instructions. Finally, the compiler was considered for use in a non-conventional role where rather than generating code it is used to apply source-level transformations prior to the generation of extension instructions and thus affect the shape of the instructions that are generated.

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Advanced Encryption Standard is new standard for data encryption and decryption.There is a lot of relevant research so far, but how to find out the suitable design according to the demand has become an important question. So we consult different improvement methods from relevant research, do the design space exploration of AES hardware circuit design with the modeling of parameterized IP Generator.We choose non-feedback mode AES design, which can offer higher security. Using the submodule as different design parameter such as SubBytes/InvSubBytes¡BMixColumns/InvMixColumns¡BKeyExpansion to form many kinds of AES hardware circuit. SubBytes/InvSubBytes¡BMixColumns/InvMixColumns module include two different structure, Integrated and Separate Encryption/Decryption module. KeyExpansion module include two different structure, on the fly and Store in Rom.There are three different keylength 128¡B192¡B256, which can form forteen different structure. We provide circuit gate count¡Bthroughput¡Bpower consumption information of different AES hardware citcuit design by the synthesis and gate-level simulation result. According to our implementation, the user can choose the suitable AES hardware circuit design method and which can solve the problem above. We also provide an automatic test pattern generator for our design verification, it makes our design can be integrated efficiently. Our experiment result show that, the design which Encryption/Decryption module use integrated structure have less circuit gate count than which Encryption/Decryption module use separate structure while throughput constraint is between 700MHz to 1300MHz (It¡¦s depend on different keylength combination). But while the throughput constraint become higher, the circuit gate count of integrated structure rise faster than separate structure. And the situation is the same with power consumption.The maximum throughput of KeyExpansion module use store in Rom structure is higher than whcich use on the fly structure.

Design Space Exploration is the task of identifying optimal implementation architectures for an application. On the front-end, it involves multi-objective optimization through a large space of options, and lends itself to a multitude of algorithmic approaches. On the back-end, it relies extensively on common capabilities such as model refinement, simulation and assessment of parameters like performance and cost. These characteristics present an opportunity to create an infrastructure that enables multiple approaches to be deployed using generic back-end services. In this work, we describe such a framework, developed using the System-on-Chip Environment, and we demonstrate the benefits and feasibility of deploying a variety of design space exploration approaches built on top of this basic infrastructure. / text

<p> Designing self-regulating machines that can see and comprehend various real world objects around it are the main purpose of the AI domain. Recently, there has been marked advancements in the field of deep learning to create state-of-the-art DNNs for various CV applications. It is challenging to deploy these DNNs into resource-constrained micro-controller units as often they are quite memory intensive. Design Space Exploration is a technique which makes CNN/DNN memory efficient and more flexible to be deployed into resource-constrained hardware. MobileNet is small DNN architecture which was designed for embedded and mobile vision, but still researchers faced many challenges in deploying this model into resource limited real-time processors.</p><p> This thesis, proposes three new DNN architectures, which are developed using the Design Space Exploration technique. The state-of-the art MobileNet baseline architecture is used as foundation to propose these DNN architectures in this study. They are enhanced versions of the baseline MobileNet architecture. DSE techniques like data augmentation, architecture tuning, and architecture modification have been done to improve the baseline architecture. First, the Thin MobileNet architecture is proposed which uses more intricate block modules as compared to the baseline MobileNet. It is a compact, efficient and flexible architecture with good model accuracy. To get a more compact models, the KilobyteNet and the Ultra-thin MobileNet DNN architecture is proposed. Interesting techniques like channel depth alteration and hyperparameter tuning are introduced along-with some of the techniques used for designing the Thin MobileNet. All the models are trained and validated from scratch on the CIFAR-10 dataset. The experimental results (training and testing) can be visualized using the live accuracy and logloss graphs provided by the Liveloss package. The Ultra-thin MobileNet model is more balanced in terms of the model accuracy and model size out of the three and hence it is deployed into the NXP i.MX RT1060 embedded hardware unit for image classification application.</p>

With ever increasing contents (safety, driver assistance, infotainment, etc.) in today's automotive systems that rely on electronics and software, the supporting architecture is integrated by a complex set of heterogeneous data networks. A modern automobile contains up to 100 ECUs and several heterogeneous communication buses (such as CAN, FlexRay, etc.), exchanging thousands of signals. The automotive Original Equipment Manufacturers (OEMs) and suppliers face a number of challenges such as reliability, safety and cost to incorporate the growing functionalities in vehicles. Additionally, reliability, safety and cost are major concerns for the industry. One of the important challenges in automotive design is the efficient and reliable transmission of signals over communication networks such as CAN and CAN-FD. With the growing features in automotives, the OEMs already face the challenge of saturation of bus bandwidth hindering the reliability of communication and the inclusion of additional features. In this dissertation, we study the problem of optimization of bandwidth utilization (BU) over CAN-FD networks. Signals are transmitted over the CAN/CAN-FD bus in entities called frames. The signal-to-frame-packing has been studied in the literature and it is compared to the bin packing problem which is known to be NP-hard. By carefully optimizing signal-to-frame packing, the CAN-FD BU can be reduced. In Chapter 3, we propose a method for offset assignment to signals and show its importance in improving BU. One of our contributions for an industrial setting is a modest improvement in BU of about 2.3%. Even with this modest improvement, the architecture's lifetime could potentially be extended by several product cycles, which may translate to saving millions of dollars for the OEM. Therefore, the optimization of signal-to-frame packing in CAN-FD is the major focus of this dissertation. Another challenge addressed in this dissertation is the reliable mapping of a task model onto a given architecture, such that the end-to-end latency requirements are satisfied. This avoids costly redesign and redevelopment due to system design errors. / Ph. D.

Indiana University-Purdue University Indianapolis (IUPUI) / Designing self-regulating machines that can see and comprehend various real world objects around it are the main purpose of the AI domain. Recently, there has been marked advancements in the field of deep learning to create state-of-the-art DNNs for various CV applications. It is challenging to deploy these DNNs into resource-constrained micro-controller units as often they are quite memory intensive. Design Space Exploration is a technique which makes CNN/DNN memory efficient and more flexible to be deployed into resource-constrained hardware. MobileNet is small DNN architecture which was designed for embedded and mobile vision, but still researchers faced many challenges in deploying this model into resource limited real-time processors. This thesis, proposes three new DNN architectures, which are developed using the Design Space Exploration technique. The state-of-the art MobileNet baseline architecture is used as foundation to propose these DNN architectures in this study. They are enhanced versions of the baseline MobileNet architecture. DSE techniques like data augmentation, architecture tuning, and architecture modification have been done to improve the baseline architecture. First, the Thin MobileNet architecture is proposed which uses more intricate block modules as compared to the baseline MobileNet. It is a compact, efficient and flexible architecture with good model accuracy. To get a more compact models, the KilobyteNet and the Ultra-thin MobileNet DNN architecture is proposed. Interesting techniques like channel depth alteration and hyperparameter tuning are introduced along-with some of the techniques used for designing the Thin MobileNet. All the models are trained and validated from scratch on the CIFAR-10 dataset. The experimental results (training and testing) can be visualized using the live accuracy and logloss graphs provided by the Liveloss package. The Ultra-thin MobileNet model is more balanced in terms of the model accuracy and model size out of the three and hence it is deployed into the NXP i.MX RT1060 embedded hardware unit for image classification application.

Formulation space exploration is a new strategy for multiobjective optimization that facilitates both divergent searching and convergent optimization during the early stages of design. The formulation space is the union of all variable and design objective spaces identified by the designer as being valid and pragmatic problem formulations. By extending a computational search into the formulation space, the solution to an optimization problem is no longer predefined by any single problem formulation, as it is with traditional optimization methods. Instead, a designer is free to change, modify, and update design objectives, variables, and constraints and explore design alternatives without requiring a concrete understanding of the design problem a priori. To facilitate this process, a new vector/matrix-based definition for multiobjective optimization problems is introduced, which is dynamic in nature and easily modified. Additionally, a set of exploration metrics is developed to help guide designers while exploring the formulation space. Finally, several examples are presented to illustrate the use of this new, dynamic approach to multiobjective optimization.

When building aircrafts, structural components must be designed for high strength, low cost, and easy assembly.To meet these conditions structural components are often based upon previous designs, even if a new component is developed.Refining previous designs can be a good way of preserving knowledge but can also limit the exploration of new design concepts. Currently the design process for structural aircraft components at SAAB is managed by design engineers. The design engineer is responsible for ensuring the design meets requirements from several different disciplines such as structural analysis, manufacturing, tool design, and assembly.Therefore, the design engineer needs to have good communication with all disciplines and an effective flow of information. The previous design is refined, it is then reviewed and approved by adjacent disciplines.Reviewing designs is an iterative process, and when several disciplines are involved it quickly becomes time consuming.Any time the design is altered it has to be reviewed once more by all disciplines to ensure the change is acceptable.So there is a need for further customizing the design concept to decrease the number of iterations when reviewing. Design Space Exploration DSE is a well known method to explore design alternatives before implementation and is used to find new concepts.This thesis investigates if DSE can be used to facilitate the design process of structural aircraft components and if it can support the flow of information between different disciplines.To find a suitable discipline to connect with design a prestudy is conducted, investigating what information affect structural design and how it is managed.The information flow is concluded in a schematic diagram where structural analysis is chosen as additional discipline. By using topology optimization in a DSE, design and structural analysis are connected.The design space can be explored with regards to structural constraints.The thesis highlights the possibilities of using DSE with topology optimization for developing structural components and proposes a method for including it in the design process.