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Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references. Available also from UMI/Dissertation Abstracts International.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.

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Thesis (M.S.)--Ohio University, June, 1983. / Title from PDF t.p.

The dissertation is a description of an analysis and a case study of an Optimization Stage for a Standard Cell oriented silicon compiler. Using the AHPL hardware description language, a complete representation hierarchy (functional, logic, and layout) is proposed for circuits defined at a Register Transfer level. The design of a new class of methods for layout analysis and optimization is based on this hierarchy. A layout evaluation method is based on the analysis of an activity graph derived from a circuit layout. The cost measure for such a graph is defined and used in evaluation of the necessary and sufficient conditions for design optimality (NSCDO). Iterations within the optimization process are controlled using a synthetic measure derived from these optimality conditions. A proposed layout optimization heuristic, derived from NSCDO, allows for better routing channel area utilization without compromising a circuit's timing performance. It is based on an analysis of the timing behavior modifications introduced by the various materials used as interconnectors resulting in an improvement of the load dependency of the output driving capabilities of cells. The dissertation contains an example of a quantitative analysis of a CMOS digital circuit. A system implementing some of the algorithms described above has been written in FORTRAN77.

This thesis describes a new test generating algorithm, depth-first algorithm. This algorithm detects the reconvergent fanout. The controllability and observability measures are included in this algorithm to guide the forward and consistency drives. The major objective of this research is to develop a test vector generatiang algorithm, which is modified from D-algorithm, and to link this algorithm with SCIRTSS programs. This depth-first algorithm is more accurate and more efficient than D-algorithm. Serveral circuits are tested under DF3 and SCR3 and the results are listed in this paper.

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Thesis (Ph. D.)--UNL/FCT. / Includes bibliographical references and index.

Thesis (Ph. D.)--UNL/FCT. / Description based on print version record. Includes bibliographical references and index.