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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
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Showing 1 to 2 of 2 (0.027 seconds)Spelling suggestions: "subject:"4digital frontend"" "subject:"4digital frontend""
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VLSI Implementation of Key Components in A Mobile Broadband ReceiverHuang, Yulin January 2009 (has links)
<p>Digital front-end and Turbo decoder are the two key components in the digital wireless communication system. This thesis will discuss the implementation issues of both digital front-end and Turbo decoder.The structure of digital front-end for multi-standard radio supporting wireless standards such as IEEE802.11n, WiMAX, 3GPP LTE is investigated in the thesis. A top-to-down design methods. 802.11n digital down-converter is designed from Matlab model to VHDL implementation. Both simulation and FPGA prototyping are carried out.As another significant part of the thesis, a parallel Turbo decoder is designed and implemented for 3GPPLTE. The block size supported ranges from 40 to 6144 and the maximum number of iteration is eight.The Turbo decoder will use eight parallel SISO units to reach a throughput up to 150Mits.</p>
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VLSI Implementation of Key Components in A Mobile Broadband ReceiverHuang, Yulin January 2009 (has links)
Digital front-end and Turbo decoder are the two key components in the digital wireless communication system. This thesis will discuss the implementation issues of both digital front-end and Turbo decoder.The structure of digital front-end for multi-standard radio supporting wireless standards such as IEEE802.11n, WiMAX, 3GPP LTE is investigated in the thesis. A top-to-down design methods. 802.11n digital down-converter is designed from Matlab model to VHDL implementation. Both simulation and FPGA prototyping are carried out.As another significant part of the thesis, a parallel Turbo decoder is designed and implemented for 3GPPLTE. The block size supported ranges from 40 to 6144 and the maximum number of iteration is eight.The Turbo decoder will use eight parallel SISO units to reach a throughput up to 150Mits.
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