The first topic of this thesis presents a novel VGA (variable gain amplifier) design which is applied in the AGC (automatic gain control) loop of digital video broadcasting - terrestrial (DVB-T) receivers. A total of three digital variable gain amplifiers (DVGA) are cascaded to provide a 70 dB dynamic range and 95 MHz operation frequency. The proposed digital VGA implemented by 0.35um 2P4M CMOS technology possesses 70 dB dynamic tuning range with a 0.3 dB gain error and 95 MHz bandwidth, and the power consumption is found to be 32.7 mW given a 3.3 V power supply. The second topic presents a design of a 60 ps peak-to-peak jitter, 80MHz, phase-locked loop (PLL) circuit for DVB-T receivers. The simulation results using the TSMC (Taiwan Semiconductor Manu-facturing Company) 0.35um 2P4M CMOS process show that the proposed PLL achieves as low as 60 ps peak-to-peak jitter when the output frequency is 80 MHz and the power consumption is merely 10.5 mW given a 3.3 V power supply.

Thesis discusses the possibility of using MEMS microphones in measuring systems. Describes the characteristics of MEMS components and shows possible realization of analog to digital signal convertor when a microphone with analog output is used. Design of the amplifier is made with respect to low noise and low power consumption. Also is shown the possibility of using antialliasing filter as microphone frequency response correction at the same time.