Discrete event systems (DES) are a special class of dynamical systems with discrete-valued state space and event-driven transitions. DES are ubiquitous in today's world and are used in different sectors such as manufacturing systems, transport networks and computer networks. They offer unique capabilities, such as flexibility and adaptability; at the same time, they can be challenging to model and analyze. Moreover, the complexity of DES is scaled up when disturbances are present. Many different kinds of real life DES can be modeled using dioid algebra which is a powerful tool for describing nonlinear behaviors using linear system models. Dioid algebra is an exotic algebra of formal series which can be understood as a set of only positive numbers without negatives. This special algebraic structure is useful in modeling DES because such systems feature variables that cannot be inverted with respect to some variables. Nonlinear behaviors of DES are able to be modeled as linear systems in terms of dioid algebra in order to use classical control techniques in scheduling and control of DES.This dissertation presents the scheduling and control of DES using a special dioid called max-plus algebra, which is a set of real numbers with the operation of maximum and addition replacing the usual classical operations of addition and multiplication, respectively. This dissertation also studies the behavior of DES when disturbances are present. Two different paths to the scheduling of DES are presented: using dioid algebra and using linear programming methods. The control of DES with disturbances and uncertainties is also explored, particularly, the solutions of the disturbance decoupling problem and the modified disturbance decoupling problem using various controller structures are presented. Disturbance decoupling in this dissertation means the scheduling of the DES will not not be affected by the presence of the disturbances. On the other hand, modified disturbance decoupling means the scheduling will not be worse than the delays caused by the disturbances in industrial just-in-time (JIT) standards. JIT means that the operations start with just enough time to be completed by the desired schedule in order to minimize waste and costs in work in progress and material storage.The applicability of the approach presented in this dissertation is demonstrated in real-world processes including a large-scale high throughput screening (HTS) system in drug discovery and an optimal scheduler for an airport's runways. The main contributions of this dissertation are max-plus and mathematical programming solutions for scheduling and control of discrete event systems with disturbances. The results present a theoretical scheduling prior to exhaustive scheduling algorithms in large-scaled industrial systems.

Indiana University-Purdue University Indianapolis (IUPUI) / In the healthcare industry, several modern patient identification and patient matching systems have been introduced. Most of these implement patient identification by their first, middle and last names. They also use Social Security Number and other similar national identifiers. These methods may not work for many developing and underdeveloped countries where identifying a patient is a challenge with highly redundant and interchangeable first and last names of the patient, this is aggravated by the absence of a national identification system. In order to make the patient identification more efficient, Muzima, an interface of OpenMRS (Open source medical records system) introduced an additional identifier, fingerprint, through a module to the system. Ordinary and Time Petri nets are used to analyze this module. Chapter 1 introduces Muzima fingerprint module and describes the workflow of this interface followed by the related work, importance and applications of Petri nets. Chapter 2 introduces Ordinary and Time Petri nets using examples. Chapter 3 discusses about the mathematical modeling of the Muzima Fingerprint module using Petri nets. Chapter 4 explains the qualitative and quantitative analysis done on the Muzima fingerprint module. Chapter 5 discusses about the programming and simulation done to prove the theoretical results obtained. Chapter 6 provides the conclusion and future work for the thesis.

This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. / This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We first introduce the sampled-data setting from Wang, and then define the sampled-data properties he identified, including the SD controllability property. We then introduce Wang's formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We then discuss Wang's modular and centralized translation method. We next introduced new modular results for the SD controllability point 3.1, SD controllability point 3.2, SD controllability point 4, activity loop free and S-singular prohibitable behaviour that allow one to verify the properties using only a portion of the system, instead of having to construct the entire system model. This should allow faster verification times as well as allow larger systems to be verified. We then introduce for the first time algorithms to verify Wang's CS Deterministic and non self-loop ALF properties. The remainder of the thesis focuses on developing algorithms and software to automatically convert a TDES first into an FSM, and then into a VERILOG module. VERILOG is a hardware description language which allows our FSM to be compiled and implemented on digital logic devices such as an FPGA. We then tested our method by modelling a simple door locking system as TDES, checking that the system satisfies the required sampled-data properties, and then translating the result into VERILOG. The above algorithms and methods have all been implemented as a part of the graphical DES research tool, DESpot. / Thesis / Master of Computer Science (MCS)

This thesis focuses on issues related to implementing theoretical Discrete-Event Systems (DES) supervisors, and the concurrency and timing delay issues involved. Sampled-data (SD) supervisory control deals with timed DES (TDES) systems where the supervisors will be implemented as SD controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states, and updates its outputs. In this thesis, we identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller. We then establish a formal representation of an SD controller as a Moore Finite State Machine (FSM), and describe how to translate a TDES supervisor to a FSM, as well as necessary properties to be able to do so. We discuss how to construct a single centralized controller, as well as a set of modular controllers and show that they will produce equivalent output. Next, we capture the enablement and forcing action of a translated controller in the form of a TDES supervisory control map, and show that the closed-loop behavior of this map and the plant is the same as that of the plant and the original TDES supervisor. We also show that our method is robust with respect to nonblocking and certain variations in the actual behavior of our physical system. We also introduce a set of predicate-based algorithms to verify the SD controllability property, as well as certain other conditions that we require. We have created a software tool for verifying these conditions and provide the source code in the appendix. We have implemented these algorithms using binary decision diagrams (BDD). For illustrative purpose, we have produced a set of examples which fail the key conditions discussed in this thesis, as well as a successful application example based on a Flexible Manufacturing System. We also presented the corresponding FSM, translated from the example's supervisors. / Thesis / Master of Applied Science (MASc)

In decentralized control, agents have only a partial view and partial control of the system and must cooperate to achieve the control objective. In order to synthesize a decentralized control solution, a specification must satisfy the co-observability property. Existing co-observability verification methods require the possibly intractable construction of the complete system. To address this issue, we introduce an incremental verification of co-observability approach. Selected subgroups of the system are evaluated individually, until verification is complete. The new method is potentially much more efficient than the monolithic approaches, in particular for systems composed of many subsystems, allowing for some intractable problems to be manageable. Properties of this new strategy are presented, along with a corresponding algorithm and an example. To further increase the scalability of decentralized control, we wish to adapt the existing Hierarchical Interface-Based Supervisory Control (HISC) to support it. We introduce the Hierarchical Interface-Based Decentralized Supervisory Control (HIDSC) framework that extends HISC to decentralized control. To adapt co-observability for HIDSC, we propose a per-component definition of co-observability along with a verification strategy that requires only a single component at a time in order to verify co-observability. Finally, we provide and prove the necessary and sufficient conditions for supervisory control existence in the HIDSC framework and illustrate our approach with an example. As the entire system model never needs to be constructed, HIDSC potentially provides significant savings. / Thesis / Doctor of Philosophy (PhD)

O objeto de estudo deste trabalho é a construção de modelos que permitam a estruturação do projeto do controle de sistemas flexíveis de manufatura que considerem não somente estados de operação normal, mas também estados anormais, isto é, em situações de falhas. Entende-se como falha o desvio de pelo menos uma propriedade do sistema que leva o mesmo a um estado de defeito, que por sua vez se define como um comportamento incomum, não projetado, do sistema sob estudo, que finalmente é manifestado como um defeito. Sistemas flexíveis de manufatura são sistemas que executam múltiplos processos visando à produção de diversos bens. O processo é um conjunto de ações de transformação que por sua parte requerem um conjunto de recursos que são compartilhados por outros processos simultaneamente. Sistemas flexíveis de manufatura envolvem um número relativamente grande de componentes, máquinas, equipamentos e operadores humanos, que interagem de maneira diversificada manipulando um grande conjunto de informação e diferentes materiais em ambientes que podem até ser agressivos. Independentemente de qualquer programa de manutenção, falhas são eventos que são possíveis de acontecer em qualquer sistema de tal natureza. Num ambiente ideal, o funcionamento de todos os componentes poderia ser monitorado com o objetivo de detectar as falhas prematuras, mas devido ao custo envolvido, isso se torna inviável. Neste sentido surge o desafio de detectar as falhas a partir da observação do contexto do funcionamento do processo, mediante a monitoração de alguns parâmetros, em geral de fácil acesso, e tomando em consideração manifestações (sintomas) das falhas de um ponto de vista qualitativo. O presente trabalho propõe a utilização de redes Bayesianas para o diagnóstico de falhas em sistemas flexíveis de manufatura. As redes Bayesianas constituem uma ferramenta útil para a representação das relações que existem entre as causas (componentes em estado de falha) e os sintomas (observações anormais do processo). A partir deste modelo, inferências podem ser feitas para o diagnóstico do sistema.Por outro lado, nos últimos anos a rede de Petri tem sido utilizada exitosamente na representação dos aspectos de controle de sistemas produtivos e particularmente de sistemas de manufatura e, desta forma, considera-se aqui tal ferramenta para a modelagem do sistema não só em condições normais de funcionamento como também para a representação do tratamento de falhas, no contexto de um sistema tolerante a anomalias do processo. Especial ênfase é dada à estruturação de uma metodologia que permita a concepção de um procedimento eficaz para a construção de modelos de controle. / The objective of the present work is the construction of models proper for the easy implementation of flexible manufacturing control systems able to handle not only with normal behavioral conditions, but with abnormal (or faulty) behavior as well. A fault is defined as a deviation of at least one system property that drives the system into an error state. An error is defined as an uncommon behavior, not expected from the system functionalities. Flexible manufacturing systems are systems that execute multiple processes for the production of several items in several ways. A process is a sequence of certain transformation tasks that require a set of resources shared simultaneously by multiple processes. In this sense, flexible manufacturing systems are constituted of a relatively great number of devices, machines, equipments and human operators that work together manipulating great quantities of information and materials. This work is usually performed in aggressive environments. So, independent of any maintenance program, faults are events that cannot be totally avoided. In an ideal environment, the monitoring of all components is the way to avoid faults. Nevertheless, due to the cost involved, this is an impossible task. In this context, there is a challenge to properly detect faults from the observation of the systems context, through the monitoring and observation of some parameters in general easy to access, including also qualitative information from operators. In the present work, it is proposed the use of Bayesian networks for the fault diagnosis in flexible manufacturing systems. Bayesian networks constitute a useful tool for the modeling of the causal relation between the causes (faulty components) and the symptoms (manifestations). Based on this model, inference can be done for the system diagnosis task. Additionally, in the last years Petri net has been successfully used for the modeling of control systems of productive systems and particularly, manufacturing control systems. In this work, beyond the use of Petri net for the modeling of normal situations of the system, Petri net is used for the modeling of the fault treatment techniques. This drives the system tolerance to faults. Especial emphasis is laid into methodological issues that allows for the structuration of a systematic procedure proper for the modeling and construction of control systems.

O presente trabalho trata da verificação e design de sistemas complexos, especificamente da verificação de sistemas de tempo real concorrentes e distribuídos. Propõe-se uma técnica enumerativa para a verificação formal de modelos que permite determinar a validade de propriedades quantitativas, além das qualitativas. A técnica proposta separa a construção do espaço de estados dos algoritmos de rotulação das fórmulas temporais, o que possibilita a diminuição da complexidade do processo de verificação, tornando-o viável para aplicações práticas. A técnica proposta foi inicialmente aplicada sobre modelos de redes de Petri temporizadas e depois em uma rede unificada chamada GHENeSys para aproveitar as características de abstração, hierarquia e de elementos de interação chamados pseudo-boxes. A definição da rede GHENeSys foi modificada para permitir a modelagem de sistemas onde os requisitos temporais devem ser expressos através de atrasos e prazos como e o caso dos sistemas de tempo real. A rede suporta ainda mecanismos de refinamento tanto para os elementos ativos quanto os passivos. A demonstração da manutenção de propriedades como invariantes, vivacidade, limitação assim como da validade de fórmulas lógicas no processo de refinamento constitui um aspecto fundamental no projeto de sistemas complexos, e foi portanto revista em detalhes para a rede GHENeSys. Alguns exemplos práticos são apresentados para avaliar o desempenho dos algoritmos e um estudo de caso finaliza a apresentação, onde se pode contrastar os algoritmos propostos com os implementados na ferramenta UPPAAL. / This work deals with the process of design and verification of complex systems, mainly real time, concurrent and distributed systems. An enumerative technique is proposed for model-checking which is capable of determining both quantitative and qualitative properties. The proposed technique detach the algorithm for labeling the formula being checked from the state space construction, allowing a better result in the verification process. This model-checking approach shows itself valuable in practical applications. This approach was first applied to systems modeled by Time Petri Nets and further extended to a unified net called GHENeSys, which includes abstraction and hierarchy concepts as well as elements for data and control interchange, called pseudo-boxes. The GHENeSys definition was modified in order to deal with systems in which temporal requirements can be expressed through delays and deadlines as in the real-time systems. The GHENeSys environment supports a refinement technique applied to both passive and active elements. Net properties like invariants, liveness, boundedness and also the validity of temporal formulas was proved to be maintained through the refinement process if some conditions are satisfied. Such characteristics are useful to deal with complex systems design. Some experiments based on well known academic articles were used to avaliate the performance of the algorithms and a case study is presented in order to compare obtained results with those obtained using the UPPAAL tool.

The factored state representation and concurrency semantics of Petri nets are closely related to those of classical planning models, yet automated planning and Petri net analysis have developed independently, with minimal and mainly unconvincing attempts at crossfertilisation. This thesis exploits the relationship between the formal reachability problem, and the automated planning problem, via Petri net unfolding, which is an attractive reachability analysis method for highly concurrent systems as it facilitates reasoning about independent sub-problems. The first contribution of this thesis is the theory of directed unfolding: controlling the unfolding process with informative strategies, for the purpose of optimality and increased efficiency. The second contribution is the application of directed unfolding to automated planning. Inspired by well-known planning heuristics, this thesis shows how problem specific information can be employed to guide unfolding, in response to the formal problem of developing efficient, directed reachability analysis methods for concurrent systems. Complimenting this theoretical work, this thesis presents a new forward search method for partial order planning which can be exponentially more efficient than state space search. Our suite of planners based on directed unfolding can perform optimal and suboptimal classical planning subject to arbitrary action costs, optimal temporal planning with respect to arbitrary action durations, and address probabilistic planning via replanning for the most likely path. Empirical results reveal directed unfolding is competitive with current state of the art automated planning systems, and can solve Petri net reachability problems beyond the reach of the original “blind” unfolding technique. / Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2008

Made available in DSpace on 2016-12-12T17:38:33Z (GMT). No. of bitstreams: 1 Daniel Gumiero Noronha Maas.pdf: 6258702 bytes, checksum: 06207c47266ccded357fbb819c6ae9bf (MD5) Previous issue date: 2014-09-09 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This work presents a multilayer architecture for fault diagnosis in embedded systems that allows a better discrimination of the type and source of the failure, providing an accurate and assertive diagnosis. This architecture contemplates the necessary interfaces to allow integration of this diagnostic framework in the embedded system and also considers the treatment of diagnostic information for recovery system actions purposes, or simply allows the externalization of such information. This work considers the diagnosers designed according to the methodology of fault diagnosis in DES modeled by automata. Once designed the diagnosers are implemented in ANSI C language through an automated software generation tool, and finally incorporated into the main product software where it intends to perform the diagnosis. This architecture diagnosis was then applied in a case study for Frost Free refrigerator, for which the diagnosers were designed then were implemented in software and subsequently validated in order to confirm the effectiveness of the diagnosers, of the proposed architecture beyond the C language conversion process. / Este trabalho apresenta uma arquitetura de diagnóstico multicamadas para detecção de falhas em sistemas embarcados, que permite uma melhor discriminação do tipo e origem da falha, possibilitando um diagnóstico mais preciso e assertivo. Esta arquitetura contempla as interfaces necessárias para permitir a integração no sistema embarcado e também considera o tratamento das informações de diagnóstico para fins de ações de recuperação do sistema, ou simplesmente a externalização destas informações. Neste trabalho, consideram-se os diagnosticadores projetados conforme a metodologia de diagnóstico de falhas em SEDs modelados por autômatos. Uma vez concebidos, os diagnosticadores são implementados em linguagem ANSI C, através de uma ferramenta de geração automática de software, e finalmente incorporados ao software principal do equipamento onde se pretende realizar o diagnóstico. Esta arquitetura de diagnóstico foi então aplicada em um estudo de caso para um refrigerador Frost Free, para o qual foram projetados os diagnosticadores, em seguida os mesmos foram implementados em software e posteriormente validados a fim de comprovar a eficácia não somente dos diagnosticadores mas também da arquitetura proposta, além do processo de conversão dos mesmos em linguagem de software.

O presente trabalho trata da verificação e design de sistemas complexos, especificamente da verificação de sistemas de tempo real concorrentes e distribuídos. Propõe-se uma técnica enumerativa para a verificação formal de modelos que permite determinar a validade de propriedades quantitativas, além das qualitativas. A técnica proposta separa a construção do espaço de estados dos algoritmos de rotulação das fórmulas temporais, o que possibilita a diminuição da complexidade do processo de verificação, tornando-o viável para aplicações práticas. A técnica proposta foi inicialmente aplicada sobre modelos de redes de Petri temporizadas e depois em uma rede unificada chamada GHENeSys para aproveitar as características de abstração, hierarquia e de elementos de interação chamados pseudo-boxes. A definição da rede GHENeSys foi modificada para permitir a modelagem de sistemas onde os requisitos temporais devem ser expressos através de atrasos e prazos como e o caso dos sistemas de tempo real. A rede suporta ainda mecanismos de refinamento tanto para os elementos ativos quanto os passivos. A demonstração da manutenção de propriedades como invariantes, vivacidade, limitação assim como da validade de fórmulas lógicas no processo de refinamento constitui um aspecto fundamental no projeto de sistemas complexos, e foi portanto revista em detalhes para a rede GHENeSys. Alguns exemplos práticos são apresentados para avaliar o desempenho dos algoritmos e um estudo de caso finaliza a apresentação, onde se pode contrastar os algoritmos propostos com os implementados na ferramenta UPPAAL. / This work deals with the process of design and verification of complex systems, mainly real time, concurrent and distributed systems. An enumerative technique is proposed for model-checking which is capable of determining both quantitative and qualitative properties. The proposed technique detach the algorithm for labeling the formula being checked from the state space construction, allowing a better result in the verification process. This model-checking approach shows itself valuable in practical applications. This approach was first applied to systems modeled by Time Petri Nets and further extended to a unified net called GHENeSys, which includes abstraction and hierarchy concepts as well as elements for data and control interchange, called pseudo-boxes. The GHENeSys definition was modified in order to deal with systems in which temporal requirements can be expressed through delays and deadlines as in the real-time systems. The GHENeSys environment supports a refinement technique applied to both passive and active elements. Net properties like invariants, liveness, boundedness and also the validity of temporal formulas was proved to be maintained through the refinement process if some conditions are satisfied. Such characteristics are useful to deal with complex systems design. Some experiments based on well known academic articles were used to avaliate the performance of the algorithms and a case study is presented in order to compare obtained results with those obtained using the UPPAAL tool.