Ferramentas de projeto de circuitos integrados (do inglˆes, electronic design automation, ou simplesmente EDA) tˆem um papel fundamental na crescente complexidade dos projetos de circuitos digitais. Elas permitem aos projetistas criar circuitos com um n´umero de componentes ordens de grandezas maior do que seria poss´ıvel se os circuitos fossem projetados `a m˜ao como nos dias iniciais da microeletrˆonica. Neste trabalho, dois importantes problemas em EDA ser˜ao abordados: dimensionamento de portas e posicionamento detalhado dirigido a desempenho. Para dimensionamento de portas, uma nova metodologia de relaxac¸ ˜ao Lagrangiana ´e apresentada baseada em informac¸ ˜ao de temporarizac¸ ˜ao locais e propagac¸ ˜ao de sensitividades. Para posicionamento detalhado dirigido a desempenho, um conjunto de movimentos de c´elulas ´e criado usando uma formac¸ ˜ao ´otima atenta `a forc¸a de alimentac¸ ˜ao para o balanceamento de cargas. Nossos resultados experimentais mostram que tais t´ecnicas s˜ao capazes de melhorar o atual estado-da-arte. / Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it would be possible by designing circuits by hand as was done in the early days of microelectronics. In this work, two important EDA problems are addressed: gate sizing and timing-driven detailed placement. They are studied and new techniques developed. For gate sizing, a new Lagrangian-relaxation methodology is presented based on local timing information and sensitivity propagation. For timing-driven detailed placement, a set of cell movement methods are created using drive strength-aware optimal formulation to driver/sink load balancing. Our experimental results shows that those techniques are able to improve the current state-of-the-art.

In today's world, it is becoming increasingly important to be able to design high performance integrated circuits (ICs) and have them run at as low power as possible. Gate sizing and threshold voltage (Vt) assignment optimizations are one of the major contributors to such trade-offs for power and performance of ICs. In fact, the ever increasing design sizes and more aggressive timing requirements make gate sizing and Vt assignment one of the most important CAD problems in physical synthesis. A promising gate sizing optimization algorithm has to satisfy requirements like being scalable to tackle very large design sizes, being able to optimally utilize a large (but finite) number of possible gate configurations available in standard cell library based on different gate sizes and/or threshold voltages (Vt) and/or gate lengths (Lg), and also, being able to handle non-convex cell delays in modern cell libraries. The work in this thesis makes use of the research-oriented infrastructure made available as part of the ISPD (International Symposium on Physical Design) 2012 Gate Sizing Contest that addresses the issues encountered in modern gate sizing problems. We present a two-phase optimization approach where Lagrangian Relaxation is used to formulate the optimization problem. In the first phase, the Lagrangian relaxed subproblem is iteratively solved using a greedy algorithm, while in the second phase, a cell downsizing and Vt upscaling heuristic is employed to further recover power from the timing-feasible and power-optimized sizing solution obtained at the end of first phase. We also propose a multi-core implementation of the first-phase optimizations, which constitute majority of the total runtime, to take advantage of multi-core processors available today. A speedup of the order of 4 to 9 times is seen on different benchmarks as compared to serial implementation when run on a 2 socket 6-core machine. Compared to the winner of ISPD 2012 contest, we further reduce leakage power by 17.21% and runtime by 87.92%, on average, while obtaining feasible sizing solutions on all the benchmark designs. / text

Ferramentas de projeto de circuitos integrados (do inglˆes, electronic design automation, ou simplesmente EDA) tˆem um papel fundamental na crescente complexidade dos projetos de circuitos digitais. Elas permitem aos projetistas criar circuitos com um n´umero de componentes ordens de grandezas maior do que seria poss´ıvel se os circuitos fossem projetados `a m˜ao como nos dias iniciais da microeletrˆonica. Neste trabalho, dois importantes problemas em EDA ser˜ao abordados: dimensionamento de portas e posicionamento detalhado dirigido a desempenho. Para dimensionamento de portas, uma nova metodologia de relaxac¸ ˜ao Lagrangiana ´e apresentada baseada em informac¸ ˜ao de temporarizac¸ ˜ao locais e propagac¸ ˜ao de sensitividades. Para posicionamento detalhado dirigido a desempenho, um conjunto de movimentos de c´elulas ´e criado usando uma formac¸ ˜ao ´otima atenta `a forc¸a de alimentac¸ ˜ao para o balanceamento de cargas. Nossos resultados experimentais mostram que tais t´ecnicas s˜ao capazes de melhorar o atual estado-da-arte. / Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it would be possible by designing circuits by hand as was done in the early days of microelectronics. In this work, two important EDA problems are addressed: gate sizing and timing-driven detailed placement. They are studied and new techniques developed. For gate sizing, a new Lagrangian-relaxation methodology is presented based on local timing information and sensitivity propagation. For timing-driven detailed placement, a set of cell movement methods are created using drive strength-aware optimal formulation to driver/sink load balancing. Our experimental results shows that those techniques are able to improve the current state-of-the-art.

Ferramentas de projeto de circuitos integrados (do inglˆes, electronic design automation, ou simplesmente EDA) tˆem um papel fundamental na crescente complexidade dos projetos de circuitos digitais. Elas permitem aos projetistas criar circuitos com um n´umero de componentes ordens de grandezas maior do que seria poss´ıvel se os circuitos fossem projetados `a m˜ao como nos dias iniciais da microeletrˆonica. Neste trabalho, dois importantes problemas em EDA ser˜ao abordados: dimensionamento de portas e posicionamento detalhado dirigido a desempenho. Para dimensionamento de portas, uma nova metodologia de relaxac¸ ˜ao Lagrangiana ´e apresentada baseada em informac¸ ˜ao de temporarizac¸ ˜ao locais e propagac¸ ˜ao de sensitividades. Para posicionamento detalhado dirigido a desempenho, um conjunto de movimentos de c´elulas ´e criado usando uma formac¸ ˜ao ´otima atenta `a forc¸a de alimentac¸ ˜ao para o balanceamento de cargas. Nossos resultados experimentais mostram que tais t´ecnicas s˜ao capazes de melhorar o atual estado-da-arte. / Electronic design automation (EDA) tools play a fundamental role in the increasingly complexity of digital circuit designs. They empower designers to create circuits with several order of magnitude more components than it would be possible by designing circuits by hand as was done in the early days of microelectronics. In this work, two important EDA problems are addressed: gate sizing and timing-driven detailed placement. They are studied and new techniques developed. For gate sizing, a new Lagrangian-relaxation methodology is presented based on local timing information and sensitivity propagation. For timing-driven detailed placement, a set of cell movement methods are created using drive strength-aware optimal formulation to driver/sink load balancing. Our experimental results shows that those techniques are able to improve the current state-of-the-art.