A computationally efficient, discrete model is presented for transmission line analysis and passive model order reduction of high-speed interconnect systems. The development of this model was motivated by the on-going efforts in chip/package co-design to route a major portion of the on-chip clock and high-speed data buses through the package in order to overcome the bandwidth reduction and delay caused by the high ohmic loss of on-chip wiring. The geometric complexity of the resulting interconnections is such that model order reduction is essential for rapid and accurate signal integrity assessment to support pre-layout design iteration and optimization. The modal network theory of the skin effect in conjunction with the theory of compact differences is used for the development of discrete models for dispersive, multi-conductor interconnects compatible with passive model order reduction algorithms. The passive reduced-order interconnect modeling algorithm, PRIMA, is then used on the resulting discrete model to generate a low-order, multi-port macromodel for interconnect networks. Numerical examples are used to demonstrate the validity and efficiency of the proposed model.