This thesis is composed of three parts. The first part surveys the literature on RF architecture and semiconductor process technology in the DVB-H tuner applications. The RFIC design considerations are also discussed. In the second part, the DVB-H tuner RFIC design using TSMC 0.18£gm RF CMOS technology is presented. Discussions between simulated and measured results of each circuit stage are also included. In the third part, the RFIC testing results for CW and DVB-H input signals are demonstrated. For a QPSK signal with 8MHz bandwidth and 7/8 code rate, the sensitivity of the RFIC can reach -87dBm. The adjacent channel protection ratio can meet the specification. The chip power consumption is 70.2mW, and the chip size is 1.96 mm2.

This thesis consisted of three parts. The first part discussed the RF architecture for the digital video broadcasting-handheld (DVB-H) system. The system planning and link budget of the RF receiver are included in this part. The effects of phase noise from local oscillator on the OFDM system are also considered here. The second part introduced the implementation of each stage for the designed receiver link. The measurement results for the entire RF receiver module are discussed in the third part, at which the link budget results are also presented for comparison. The sensitivity of the designed RF receiver module is -83 dBm, the dynamic range is more than 73 dB, and the power consumption is 345 mW. The designed RF receiver adopts the dual conversion with zero second IF architecture reduces the number of ICs, passive components, and the power consumption. In addition, the SAW filter is no longer required in the receiver link, and it is more suitable for the system-on-chip application.