The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3¡ÑVDD wide range fully bidirectional mixed-voltage-tolerant I/O cell. The first topic discloses a mixed-voltage-tolerant I/O cell implemented using 2P4M 0.35 £gm CMOS process, which uses a low static power dynamic gate bias generator providing three different logic voltage levels to the output stage to avoid gate oxide reliability and leakage current. The design also reveals a new output stage circuit, which enhances the output current to resolve the poor driving capability caused by the slow mobility and body effect of the stacked PMOS. The second topic shows a sub-3¡ÑVDD wide range fully bidirectional mixed-voltage-tolerant I/O cell using 1P6M 0.18 £gm CMOS process, which employs a new dynamic gate bias generator and a PAD voltage detector to provide appropriate gate biases. The design includes a new gate tracking circuit and a floating N-well circuit to avoid gate oxide reliability and leakage current, which relaxes the body effect at the output PMOS.

In modern wireless communication systems, a base station typically serves a few hundred users within its cell coverage. To combat the near-far problem – the situation where a nearby user’s strong cellular signal masks the cellular signal of a faraway user – base stations continually enforce power control. That is, nearby users must lower their transmit power. In CDMA technology, power control can be as large as 70-80dB. At low power outputs, this greatly impacts the performance of the RF power amplifier (PA) in the cellular device. For small RF drives, the magnitude of the output RF current approaches the magnitude of the DC current and thus the efficiency suffers. Operating the RF PA in class C operation improves the efficiency, but results in poor linearity. Several methods of so-called dynamic biasing have been proposed. These strategies entail lowering the bias of the PA as the RF drive increases. The proposed methods, however, fail to explain how to achieve linearity and low third-order intermodulation distortion. Additionally, the methods utilize open-loop implementations. This work presents a novel dynamic biasing topology that results in a much improved linear class C PA. The topology utilizes a closed loop that cleverly senses the operating conditions of the "power device." Particularly, the loop operates on the principle of keeping the conduction angle remarkably constant and thereby ensuring linearity. The work details a thorough design methodology that should provide assistance to a designer wanting to implement the topology in an RF integrated circuit. Agilent ADS simulations and laboratory results from a functional PCB prototype bring merit to the topology.

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018