Attacks on the heap are an increasingly severe threat. State-of-the-art secure dynamic memory allocators can offer protection, however their memory consumption is high, making them suboptimal in many situations. We introduce sys, a secure allocator whose design is driven by memory efficiency. Among other features, sys uses an efficient fine-grain size classes indexing mechanism and implements a novel dynamic canary scheme. It offers a low memory overhead due its size classes optimized for canary usage, its on-demand metadata allocation, and the combination of randomized allocations and over-provisioning into a single memory efficient security feature. sys protects against widespread heap-related attacks such as overflows, over-reads, double/invalid free, and use-after-free. Evaluation over a wide range of applications shows that it offers a significant reduction in memory consumption compared to the state-of-the-art secure allocator (up to 2x in macro-benchmarks), while offering similar or better security guarantees and good performance. / Master of Science / Attacks targeting on the runtime memory (heap allocator) are severe threats to software safety. Statistical results shown that the numbers of heap-related attacks has doubled since 2016. A large number of research works are designed to solve the security problems by offering different techniques to prevent some specific attacks. Not only are they very secure but also fast. However, these secure heap allocators sacrifice the memory usage, all of them at least double the memory consumption. Our work is trying to design and implement a heap allocator, in which it can defend against different attacks, as well as fast and memory-efficient. We carefully re-design some security features in our heap allocator while keep memory-efficient in mind. In the end, we evaluated sys and found that it offers significant reduction on different benchmarks suites. Evaluation also showed that sys can detect a lot of vulnerabilities in the software, while offer the same good performance as the state-of-the-art heap allocator.

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Dynamic memory allocators are a determining factor of an application's performanceand have the opportunity to improve a major performance bottleneck ontoday's computer hardware: data locality. To approach this problem, a memoryallocator must rst oer strategies that allow the locality problem to be addressed.However, while focusing on locality, an allocator must also not ignore the existing constraintsof allocation speed and fragmentation, which further complicate its design. Inorder for a locality improving technique to be successfully employed in today's largecode applications, its integration needs to be automatic, without user intervention.The alternative, manual integration, is not a tractable solution.In this dissertation we develop three novel memory allocators that explore dierentallocation strategies that enhance an application's locality. We conduct the rststudy that shows that allocation speed, fragmentation and locality improving goalsare antagonistic. We develop an automatic method that supplies allocation hintsfrom C++ STL containers to their allocators. This method allows applications tobenet from locality improving techniques at the cost of a simple re-compilation. Weconduct the rst study that quanties the eect of allocation hints on performance,and show that an allocator with high locality of reference can be as competitive asone using an application's spatial feedback.To further allow dynamic memory allocation to improve an application's performance,new and non-traditional strategies need be explored. We develop a generic software tool that allows users to examine unconventional strategies. The tool allowsusers not only to focus on allocation strategies rather than their implementation, butalso to compare and contrast various approaches.

Dynamic memory allocators are a determining factor of an application's performanceand have the opportunity to improve a major performance bottleneck ontoday's computer hardware: data locality. To approach this problem, a memoryallocator must rst oer strategies that allow the locality problem to be addressed.However, while focusing on locality, an allocator must also not ignore the existing constraintsof allocation speed and fragmentation, which further complicate its design. Inorder for a locality improving technique to be successfully employed in today's largecode applications, its integration needs to be automatic, without user intervention.The alternative, manual integration, is not a tractable solution.In this dissertation we develop three novel memory allocators that explore dierentallocation strategies that enhance an application's locality. We conduct the rststudy that shows that allocation speed, fragmentation and locality improving goalsare antagonistic. We develop an automatic method that supplies allocation hintsfrom C++ STL containers to their allocators. This method allows applications tobenet from locality improving techniques at the cost of a simple re-compilation. Weconduct the rst study that quanties the eect of allocation hints on performance,and show that an allocator with high locality of reference can be as competitive asone using an application's spatial feedback.To further allow dynamic memory allocation to improve an application's performance,new and non-traditional strategies need be explored. We develop a generic software tool that allows users to examine unconventional strategies. The tool allowsusers not only to focus on allocation strategies rather than their implementation, butalso to compare and contrast various approaches.

Moore's law states that the amount of computational power available at a given cost doubles every 18 months and indeed, for the past 20 years there has been a tremendous development in microprocessors. However, for the last few years, Moore's law has been subject for debate, since to manage heat issues, processor manufacturers have begun favoring multicore processors, which means parallel computation has become necessary to fully utilize the hardware. This also means that software has to be written with multiprocessing in mind to take full advantage of the hardware, and writing parallel software introduces a whole new set of problems. For the last couple of years, the demands on telecommunication systems have increased and to manage the increasing demands, multiprocessor servers have become a necessity. Applications must fully utilize the hardware and such an application is the Diameter Credit Control Application (DCCA). The DCCA uses the Diameter networking protocol and the DCCA's purpose is to provide a framework for real-time charging. This could, for instance, be to grant or deny a user's request of a specific network activity and to account for the eventual use of that network resource. This thesis investigates whether it is possible to develop a Diameter Credit Control Application that achieves linear scaling and the eventual pitfalls that exist when developing a scalable DCCA server. The assumption is based on the observation that the DCCA server's connections have little to nothing in common (i.e. little or no synchronization), and introducing more processors should therefore give linear scaling. To investigate whether a DCCA server's performance scales linearly, a prototype has been developed. Along with the development of the prototype, constant performance analysis was conducted to see what affected performance and server scalability in a multiprocessor DCCA environment. As the results show, quite a few factors besides synchronization and independent connections affected scalability of the DCCA prototype. The results show that the DCCA prototype did not always achieve linear scaling. However, even if it was not linear, certain design decisions gave considerable performance increase when more processors were introduced.

Cette thèse est une contribution à la spécification et à la vérification formelles des allocateurs de mémoire dynamiques séquentiels (SDMA, en abrégé), qui sont des composants clés des systèmes d'exploitation ou de certaines bibliothèques logiciel. Les SDMA gèrent la partie tas de la mémoire des processus. Leurs implémentations utilisent à la fois des structures de données complexes et des opérations de bas niveau. Cette thèse se concentre sur les SDMA qui utilisent des structures de données de type liste pour gérer les blocs du tas disponibles pour l'allocation (SDMA à liste).La première partie de la thèse montre comment obtenir des spécifications formelles de SDMA à liste en utilisant une approche basée sur le raffinement. La thèse définit une hiérarchie de modèles classés par la relation de raffinement qui capture une grande variété de techniques et de politiques employées par le implémentations réelles de SDMA. Cette hiérarchie forme une théorie algorithmique pour les SDMA à liste et pourrait être étendue avec d'autres politiques. Les spécifications formelles sont écrites en Event-B et les raffinements ont été prouvés en utilisant la plateforme Rodin. La thèse étudie diverses applications des spécifications formelles obtenues: le test basé sur des modèles, la génération de code et la vérification.La deuxième partie de la thèse définit une technique de vérification basée sur l'interprétation abstraite. Cette technique peut inférer des invariants précis des implémentations existantes de SDMA. Pour cela, la thèse définit un domaine abstrait dont les valeurs representent des ensembles d'états du SDMA. Le domaine abstrait est basé sur un fragment de la logique de séparation, appelé SLMA. Ce fragment capture les propriétés liées à la forme et au contenu des structures de données utilisées par le SDMA pour gérer le tas. Le domaine abstrait est défini comme un produit spécifique d'un domaine abstrait pour graphes du tas avec un domaine abstrait pour des sequences finies d'adresses mémoire. Pour obtenir des valueurs abstraites compactes, la thèse propose une organisation hiérarchique des valeurs abstraites: un premier niveau abstrait la liste de tous les blocs mémoire, alors qu'un second niveau ne sélectionne que les blocs disponibles pour l’allocation. La thèse définit les transformateurs des valeurs abstraites qui capturent la sémantique des instructions utilisées dans les implémentations des SDMA. Un prototype d'implémentation de ce domaine abstrait a été utilisé pour analyser des implémentations simples de SDMA. / The first part of the thesis demonstrates how to obtain formal specifications of free-list SDMA using a refinement-based approach. The thesis defines a hierarchy of models ranked by the refinement relation that capture a large variety of techniques and policies employed by real-work SDMA. This hierarchy forms an algorithm theory for the free-list SDMA and could be extended with other policies. The formal specifications are written in Event-B and the refinements have been proved using the Rodin platform. The thesis investigates applications of the formal specifications obtained, such as model-based testing, code generation and verification.The second part of the thesis defines a technique for inferring precise invariants of existing implementations of SDMA based abstract interpretation. For this, the thesis defines an abstract domain representing sets of states of the SDMA. The abstract domain is based on a fragment of Separation Logic, called SLMA. This fragment captures properties related with the shape and the content of data structures used by the SDMA to manage the heap. The abstract domain is defined as a specific product of an abstract domain for heap shapes with an abstract domain for finite arrays of locations. To obtain compact elements of this abstract domain, the thesis proposes an hierarchical organisation of the abstract values: a first level abstracts the list of all chunks while a second level selects only the chunks available for allocation. The thesis defines transformers of the abstract values that soundly capture the semantics of statements used in SDMA implementations. A prototype implementation of this abstract domain has been used to analyse simple implementations of SDMA

This diploma thesis presents a tool for dynamic memory allocator analysis, focused on their performance. The work identifies the important memory allocator performance metrics, as well as the environment and program factors influencing these metrics. Using this knowledge, a tool was designed and implemented. This tool allows to gather and analyze these metrics. The tool provides the ability to create memory allocator usage scenarios for the purpose of the allocator behavior analysis under different conditions. The tool was tested on several available memory allocators with free license.

Emergent systems in high-performance computing (HPC) expect maximal efficiency to achieve the goal of power budget under 20-40 megawatts for 1 exaflop set by the Department of Energy. To optimize efficiency, emergent systems provide multiple power-performance control techniques to throttle different system components and scale of concurrency. In this dissertation, we focus on three throttling techniques: CPU dynamic voltage and frequency scaling (DVFS), dynamic memory throttling (DMT), and dynamic concurrency throttling (DCT). We first conduct an empirical analysis of the performance and energy trade-offs of different architectures under the throttling techniques. We show the impact on performance and energy consumption on Intel x86 systems with accelerators of Intel Xeon Phi and a Nvidia general-purpose graphics processing unit (GPGPU). We show the trade-offs and potentials for improving efficiency. Furthermore, we propose a parallel performance model for coordinating DVFS, DMT, and DCT simultaneously. We present a multivariate linear regression-based approach to approximate the impact of DVFS, DMT, and DCT on performance for performance prediction. Validation using 19 HPC applications/kernels on two architectures (i.e., Intel x86 and IBM BG/Q) shows up to 7% and 17% prediction error correspondingly. Thereafter, we develop the metrics for capturing the performance impact of DVFS, DMT, and DCT. We apply the artificial neural network model to approximate the nonlinear effects on performance impact and present a runtime control strategy accordingly for power capping. Our validation using 37 HPC applications/kernels shows up to a 20% performance improvement under a given power budget compared with the Intel RAPL-based method. / Ph. D. / System efficiency on high-performance computing (HPC) systems is the key to achieving the goal of power budget for exascale supercomputers. Techniques for adjusting the performance of different system components can help accomplish this goal by dynamically controlling system performance according to application behaviors. In this dissertation, we focus on three techniques: adjusting CPU performance, memory performance, and the number of threads for running parallel applications. First, we profile the performance and energy consumption of different HPC applications on both Intel systems with accelerators and IBM BG/Q systems. We explore the trade-offs of performance and energy under these techniques and provide optimization insights. Furthermore, we propose a parallel performance model that can accurately capture the impact of these techniques on performance in terms of job completion time. We present an approximation approach for performance prediction. The approximation has up to 7% and 17% prediction error on Intel x86 and IBM BG/Q systems respectively under 19 HPC applications. Thereafter, we apply the performance model in a runtime system design for improving performance under a given power budget. Our runtime strategy achieves up to 20% performance improvement to the baseline method.

The subject of the thesis is a research focused on the part of dynamic spatial memory. In the research there have been made simple scenarios, which were carried out by a selected group of four year old children. Objective of the work is to determine the extent of dynamic spatial memory in the sample of four year old children on the basis of obtained theoretical knowledge. Furthermore, to determine the quality of dynamic spatial memory in four year old children and find extent of remembering instructions (mixed communication). Based on the research findings to contribute to the improvement of professional competence kindergarten teachers working in the field of cognitive processes, without which mathematical thinking could not be developed properly. The expected outcome of the thesis is the preparation of documents designated for kindergarten teachers, which would provide them with an instructive view of examined issue. The content of work is also notification of possible cause dissonance theory and resulting analyses and proposals of corrective measures that belong to kindergarten teacher competence.

Optimized memory management is important for a demanding application to achieve high-performance results. But un-optimized or unwanted memory behaviors can usually be difficult to detect without an overview of how memory is structured during run-time. This thesis explores real-time visualization of dynamic memory allocation for applications using the memory pool allocation technique. In the thesis, technical and graphical challenges are described together with their solutions and the design choices that were made. The final result is a program that can visualize dynamic memory management in real time, with the focus on displaying a detailed and comprehensive memory overview that preserves the level of detail over time. / Optimerad minneshantering är viktig för att uppnå hög prestanda i en krävande applikation. Men att upptäcka icke optimerade eller oönskade minnesbeteenden kan vara svårt utan en visuell översikt över hur minnet är strukturerat under programmets exekvering. Denna avhandling undersöker hur dynamisk minnesallokering kan visualiseras i realtid för applikationer som använder allokeringstekniken minnes\-pool. I avhandlingen beskrivs tekniska och grafiska utmaningar tillsammans med deras lösningar och de designval som gjordes. Slutresultatet är ett program som kan visualisera dynamisk minneshantering i realtid och som fokuserar på att visa en detaljerad och omfattande minnesöversikt som bevarar detaljeringsgraden över tiden.