• Refine Query
  • Source
  • Publication year
  • to
  • Language
  • 1
  • Tagged with
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • 1
  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Dynamically controlling the clock frequency based on the variations in the voltage

Chhatbar, Jigar Chandrakant 21 December 2010 (has links)
A digital logic circuit tends to become slower if the voltage (VDD) level drops below the normal VDD level. Because of this, the required data will not have settled before the arrival of the clock edge. This results in an incorrect sampling of the data leading to a functional failure of the chip. This thesis proposes a clock controller circuit which solves this issue. It consists of a voltage monitoring circuit to track the variations in the VDD level, a frequency multiplier and divider, and a selector logic circuit that outputs a particular frequency depending upon the VDD range in which the chip is operating. / text

Page generated in 0.1166 seconds