No description available.

Supplemental passive dampers are generally considered as an effective tool to control the seismic response of multi-storey buildings. Since the optimum placement of passive dampers in buildings can potentially improve the structural performance or reduce construction cost, there is an increasing number of researchers engaged to optimize the damper placement in buildings. Given that a large number of studies have been conducted to investigate damper placement methods, a systematic method or a clear conclusion for strategically distributing dampers in buildings is not presented in any building guidelines. The main limitations of current damper placement studies may include the lack of focus on collapse resistance of retrofitted buildings, on beam and column nonlinear behaviors, and the lack of considering the variations of earthquake characteristics and intensity levels. The fundamental damper placement issue can be separated as the distribution of dampers throughout the height of the buildings and the distribution of dampers in different bays in building frames. In this research, both distributions are explored and their effect on the collapse performances of buildings under strong earthquakes is thoroughly studied. The effectiveness of advanced damper placement approaches is evaluated by comparisons with classical damper placement methods. Considering the uncertainty in earthquake ground motion characteristics, multiple ground motions scaled to various intensity levels are involved to evaluate the seismic performance of buildings. Finally, major conclusions towards the philosophy of the strategic damper placement in practical building constructions are presented in terms of the overall structural performance under strong ground motions.

Integrating learning and work has become important for several reasons. The recognition that the key resources for wealth creation, knowledge and ideas are embedded in human capital. Furthermore, fast-paced advances in knowledge, technology, and access to information ensure that capabilities rapidly become obsolete. Continuous learning and workplace learning have therefore become essential. These developments have highlighted the pivotal role of learning in individual career development and organisational performance and the construction industry needs to address these issues. The construction industry, however, continues to report skill gaps suggesting that construction businesses need to consider creative ways to deliver skill-enhancing opportunities for their workforce. The challenge is global but has added significance for African emerging economies considering their developmental needs. Integrating workforce learning and development key practices into construction business was therefore the crux of this research which was aimed at developing a conceptual learning model that will enable construction firms to optimise performance in line with their business goals. Given the complexity of the construction domain and the need to allow integration of diverse processes, perceptions, experiences, practices and interactions, a pragmatic philosophical lens was employed allowing for a mixed methods research approach. A social constructionist ontology and a largely interpretivist stance was adopted. Surveys and case studies were conducted employing questionnaires, interviews and focus group discussions for data collection. Data analysis methods used were relative importance, correlational and constant comparative analyses. The research investigated the two main elements of learning systems the learner and the learning environment. The learner aspect found that emotional and social attributes were significantly associated with the performance of intermediate construction skills while key workforce practices emerged from the learning environment studies. These findings were integrated to develop the construction learning and development optimising model (CLEARDO). The research was limited to Nigeria because of its current focal position in the African economy.

Reinforcement corrosion is one of the major causes of deterioration of reinforced concrete structures exposed to aggressive environments. Deterioration caused by reinforcement corrosion reduces the serviceability and load bearing capacity of the concrete structures to an extent of serious structural failure. Consequently, this increases the resources required for the maintenance and rehabilitation over time. Due to uncertainties associated with the performance deterioration, it is difficult to accurately assess the residual strength and remaining useful life of corrosion damaged concrete structure. Therefore, the reliability-based performance assessment techniques based on stochastic deterioration modelling has significant potential for assessing the present and future performance of these structures. This can be ultimately helpful in sustainable and cost-effective infrastructure management. This research presents new analytical methods for evaluating concrete crack evolution, estimating rebar bond strength degradation and predicting residual flexural strength of concrete structures affected by reinforcement corrosion. At first, cracking in cover concrete due to reinforcement corrosion is investigated by using rebar-concrete model and realistic concrete properties. The bond strength evolution of the corroded rebar is then evaluated at different stages of cover cracking by considering adhesion, confinement and corrosion pressure acting at the bond interface. Furthermore, the residual flexural strength of concrete beams is predicted with consideration of bond failure between the rebar and concrete. The gamma process is adopted for stochastic modelling of concrete crack growth and strength deterioration with uncertainties. Then, a time-dependent reliability analysis is undertaken to evaluate the probability of failure in serviceability and load carrying capacity of corrosion damaged concrete beams. Optimal repair planning during the service life is also determined by balancing the cost for maintenance and the risk of structural failure. Finally, the results evaluated from the proposed methods are examined by available experimental and field data and the applicability is demonstrated by numerical examples. The results obtained show that the proposed methods are capable of evaluating the performance and can also provide risk-cost balanced repair strategy during the lifetime of corrosion damaged concrete structures. The knowledge gained from this research contributes to the better understanding of the mechanics of performance deterioration associated with reinforcement corrosion. Furthermore, the methods presented in this study could be helpful in assessing the actual state of performance deterioration and making decision regarding the optimal repair.

Wong Fai-leung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 86-89). / Abstracts in English and Chinese. / ABSTRACT --- p.II / 摘要 --- p.III / ACKNOWLEDGMENT --- p.IV / TABLE OF CONTENTS --- p.V / TABLE OF FIGURES --- p.VII / Chapter 1 --- INTRODUCTION --- p.1 / Chapter 2 --- BASIC THEORY OF BRANCH LINE COUPLER --- p.4 / Chapter 2.1 --- Four-port network --- p.4 / Chapter 2.2 --- Even-odd mode analysis --- p.5 / Chapter 2.2.1 --- Even mode excitation --- p.6 / Chapter 2.2.2 --- Odd mode excitation --- p.7 / Chapter 2.2.3 --- Mathematical analysis --- p.9 / Chapter 2.3 --- Simulation results --- p.12 / Chapter 3 --- REVIEW OF ADVANCED BRANCH LINE COUPLER DESIGNS --- p.15 / Chapter 3.1 --- Broad-band uniplanar branch-line design --- p.15 / Chapter 3.2 --- Compact branch-line couplers using slow-wave structure --- p.17 / Chapter 3.3 --- Miniature branch-line coupler using eight two-step stubs --- p.18 / Chapter 3.4 --- Wide band lumped-element 3-dB quadrature coupler --- p.20 / Chapter 3.5 --- Dual band branch line coupler design using left-handed transmission lines --- p.22 / Chapter 4 --- DESIGN THEORY OF DUAL BAND BRANCH LINE COUPLERS --- p.24 / Chapter 4.1 --- design 1 - dual band branch line coupler with sub-optimum performance --- p.25 / Chapter 4.1.1 --- Analysis and design --- p.26 / Chapter 4.1.2 --- Size comparison --- p.30 / Chapter 4.2 --- Design 2 - dual band branch line coupler using shunt stubs --- p.34 / Chapter 4.2.1 --- Analysis and design --- p.35 / Chapter 4.2.2 --- Size comparison --- p.41 / Chapter 5 --- SIMULATION VERIFICATION --- p.44 / Chapter 5.1 --- Design 1 --- p.44 / Chapter 5.1.1 --- Schematic simulation --- p.45 / Chapter 5.1.2 --- Schematic simulation with line width deviation --- p.48 / Chapter 5.1.3 --- Schematic simulation with junction discontinuity --- p.54 / Chapter 5.2 --- Design 2 --- p.58 / Chapter 5.2.1 --- Schematic simulation --- p.58 / Chapter 5.2.2 --- Schematic simulation with line width deviation --- p.62 / Chapter 5.2.3 --- Schematic simulation with junction discontinuity --- p.68 / Chapter 6 --- CIRCUIT IMPLEMENTATION AND CHARACTERIZATION --- p.74 / Chapter 6.1 --- Design 1 --- p.74 / Chapter 6.1.1 --- Circuit fabrication --- p.74 / Chapter 6.1.2 --- Measurement results --- p.75 / Chapter 6.2 --- Design 2 --- p.78 / Chapter 6.2.1 --- Circuit fabrication --- p.78 / Chapter 6.2.2 --- Measurement results --- p.79 / Chapter 7 --- CONCLUSIONS --- p.83 / Chapter 8 --- RECOMMENDATIONS FOR FUTURE WORK --- p.85 / Chapter 9 --- REFERENCES --- p.86 / Chapter 10 --- AUTHOR'S PUBLICATIONS --- p.90

Chan Wing-kin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 69-72). / Abstracts in English and Chinese. / Abstract of this thesis entitled: --- p.ii / 摘要 --- p.iv / Acknowledgements --- p.v / Table of Contents --- p.vi / List of Figures --- p.viii / List of Tables --- p.x / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview of Communication Systems --- p.1 / Chapter 1.2 --- Soft-output Viterbi Decoder and Turbo Code --- p.2 / Chapter 1.3 --- Iterative Decoding --- p.3 / Chapter 1.4 --- Motivation --- p.3 / Chapter 1.5 --- Organization of the Thesis --- p.4 / Chapter Chapter 2 --- Self-timed Circuit Design Methodology --- p.5 / Chapter 2.1 --- Properties of Self-Timed Design --- p.5 / Chapter 2.2 --- Bundled-data Protocol --- p.7 / Chapter 2.3 --- Two-phase verses Four-phase Handshaking --- p.8 / Chapter 2.4 --- Completion-Detection and Delay Match --- p.9 / Chapter 2.5 --- Muller Pipeline --- p.11 / Chapter 2.6 --- Design of the Adder --- p.12 / Chapter 2.6.1 --- Basic Structure --- p.12 / Chapter 2.6.2 --- Carry Chain and Completion Detection --- p.12 / Chapter Chapter 3 --- SOVA Theory --- p.15 / Chapter 3.1 --- Convolutional Encoder --- p.15 / Chapter 3.2 --- Hard verse Soft Decision Decoding --- p.17 / Chapter 3.3 --- Soft Output Viterbi Algorithm --- p.17 / Chapter 3.3.1 --- Viterbi Algorithm --- p.17 / Chapter 3.3.2 --- Soft Output Algorithm --- p.20 / Chapter Chapter 4 --- Proposed SOVA Decoder Design --- p.24 / Chapter 4.1 --- Overview --- p.24 / Chapter 4.2 --- SOVA Decoder Architecture --- p.24 / Chapter 4.3 --- Branch Metric Unit --- p.26 / Chapter 4.3.1 --- Branch Metric Generation --- p.26 / Chapter 4.3.2 --- Implementation --- p.27 / Chapter 4.4 --- Add-Compare-Select Unit --- p.28 / Chapter 4.4.1 --- Basics --- p.28 / Chapter 4.4.2 --- Self-timed design --- p.28 / Chapter 4.4.3 --- Metric Normalization --- p.30 / Chapter 4.4.4 --- ACS Unit Implementation --- p.31 / Chapter 4.5 --- Traceback Unit --- p.33 / Chapter 4.5.1 --- Viterbi Algorithm Traceback --- p.33 / Chapter 4.5.2 --- Two Step SOVA --- p.34 / Chapter 4.5.3 --- Past Designs --- p.36 / Chapter 4.5.4 --- New Traceback Architecture --- p.38 / Chapter 4.5.5 --- Traceback operation --- p.40 / Chapter 4.5.6 --- Traceback Implementation --- p.42 / Chapter 4.5.7 --- Control Signals --- p.48 / Chapter Chapter 5 --- Experimental Result and Discussion --- p.54 / Chapter 5.1 --- Chip Fabrication --- p.54 / Chapter 5.2 --- Measurements --- p.61 / Chapter Chapter 6 --- Conclusion --- p.67 / References --- p.69 / Appendix --- p.73 / Pin Assignment of the SOVA test chip --- p.73

Tang Tze Yeung Eric. / Thesis submitted in: July 2003. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 69-75). / Abstracts in English and Chinese. / ABSTRACT --- p.II / ACKNOWLEDGMENT --- p.II / Chapter 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Embedded System --- p.1 / Chapter 1.2 --- Embedded Processor --- p.1 / Chapter 1.3 --- Embedded System Design --- p.3 / Chapter 1.3.1 --- Current Embedded System Design Challenges --- p.3 / Chapter 1.3.2 --- Embedded System Design Trend --- p.4 / Chapter 1.4 --- Efficient Software Development for Microprocessor --- p.8 / Chapter 1.4.1 --- Efficient Software Development Methodology --- p.8 / Chapter 1.5 --- Thesis Organization --- p.10 / Chapter 2 --- SOURCE CODE OPTIMIZATION --- p.11 / Chapter 2.1 --- Source Code Optimization Strategy --- p.11 / Chapter 2.2 --- Source Code Transformations --- p.12 / Chapter 2.2.1 --- Strength Reduction --- p.12 / Chapter 2.2.2 --- Function Inlining --- p.13 / Chapter 2.2.3 --- Table Lookup --- p.13 / Chapter 2.2.4 --- Loop Transformations --- p.13 / Chapter 2.2.5 --- Software Pipelining --- p.15 / Chapter 2.2.6 --- Register Allocation --- p.17 / Chapter 2.3 --- Case Study: Source Code Optimization on the StrongARM (SA1110) Platform --- p.18 / Chapter 2.3.1 --- StrongARM architecture --- p.18 / Chapter 2.3.2 --- StrongARM pipeline hazard illustration --- p.20 / Chapter 2.3.3 --- Source Code Optimization on StrongARM --- p.21 / Chapter 2.3.4 --- Instruction Set Optimization of StrongARM --- p.27 / Chapter 2.4 --- Conclusion --- p.32 / Chapter 3 --- FLOAT-TO-FIXED OPTIMIZATION --- p.33 / Chapter 3.1 --- Introduction to Fixed-point --- p.34 / Chapter 3.1.1 --- Fixed-point representation --- p.34 / Chapter 3.1.2 --- Fixed-point implementation --- p.35 / Chapter 3.1.3 --- Mathematical functions implementation --- p.38 / Chapter 3.2 --- Case Study: Fingerprint Minutiae Extraction Algorithms on the Strong ARM platform --- p.41 / Chapter 3.2.1 --- Fingerprint Verification Overview --- p.42 / Chapter 3.2.2 --- Fixed-point Implementation of Fingerprint Minutiae Extraction Algorithm --- p.49 / Chapter 3.2.3 --- Experimental Results --- p.51 / Chapter 3.3 --- Conclusion --- p.56 / Chapter 4 --- DOMAIN SPECIFIC OPTIMIZATION --- p.57 / Chapter 4.1 --- Case Study: Font Rasterization on the Strong ARM platform --- p.57 / Chapter 4.1.1 --- Outline Font --- p.57 / Chapter 4.1.2 --- Font Rasterization --- p.59 / Chapter 4.1.3 --- Experiments --- p.63 / Chapter 4.2 --- Conclusion --- p.66 / Chapter 5 --- CONCLUSION --- p.67 / BIBLIOGRAPHY --- p.69

Lee Ming Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 78-80). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1. --- Background on development of AA size micro power generator --- p.1 / Chapter 1.1.1. --- Brief introduction --- p.1 / Chapter 1.1.2. --- Proposed micro power generator for wireless applications --- p.2 / Chapter 1.2. --- Literature survey --- p.3 / Chapter 1.2.1. --- Comparison of other energy sources --- p.3 / Chapter 1.2.2. --- An overview of research on electromagnetic micro power generator --- p.5 / Chapter Chapter 2 --- Principle of Micro Power Generator --- p.7 / Chapter 2.1 --- Design objective ofAA size micro power generator --- p.7 / Chapter 2.2 --- Faraday ´ةs Law of induced current --- p.9 / Chapter 2.3 --- Modal for the micro power generator system --- p.10 / Chapter 2.4 --- Design of the micro power generator --- p.13 / Chapter 2.5 --- Integrated power cell --- p.20 / Chapter Chapter 3 --- MEMS Resonator --- p.23 / Chapter 3.1. --- Design of the micro resonator --- p.23 / Chapter 3.1.1. --- Introduction to micro resonator --- p.23 / Chapter 3.1.2. --- Selection of material --- p.24 / Chapter 3.1.3. --- Different modes of vibration --- p.25 / Chapter 3.2. --- Laser Micro-machining --- p.26 / Chapter 3.3. --- MEMS Fabricated Spring --- p.28 / Chapter 3.3.1. --- Introduction of SU-8 based electroplating technique --- p.28 / Chapter 3.3.2. --- Fabrication process --- p.31 / Chapter Chapter 4 --- Characteristic of AA Size Micro Power Generator --- p.33 / Chapter 4.1. --- Experiment on a single micro power transducer --- p.36 / Chapter 4.1.1. --- Testing a single transducer without loading --- p.37 / Chapter 4.1.2. --- Testing a single transducer connected with a power management circuit --- p.38 / Chapter 4.1.3. --- Testing a single transducer with power management circuit and a 100kΩ resistor --- p.39 / Chapter 4.1.4. --- Summary of experiments on the micro power transducer --- p.40 / Chapter 4.2. --- Experiment on finding a way to increase power output --- p.41 / Chapter 4.3. --- Experiment for connecting two micro power transducers --- p.43 / Chapter 4.3.1. --- Testing on two micro power transducers connected in series --- p.44 / Chapter 4.3.2. --- Testing on combined micro power transducers with power management circuit --- p.47 / Chapter 4.4. --- Experiment on the integrated AA size micro power generator --- p.49 / Chapter 4.4.1. --- Interaction of magnetic dipole between two micro power transducers --- p.50 / Chapter 4.4.2. --- AA size micro power generator under varying input vibration frequencies --- p.52 / Chapter Chapter 5 --- Simulation and Analysis --- p.55 / Chapter 5.1. --- FEA Modeling of the MEMS Resonators --- p.55 / Chapter 5.2. --- Micro power generator system modeling --- p.57 / Chapter 5.3. --- Optimization --- p.60 / Chapter Chapter 6 --- Applications --- p.63 / Chapter 6.1. --- Wireless Temperature Sensing System --- p.64 / Chapter 6.2. --- Measurement of car vibration for noval applications --- p.70 / Chapter 6.2.1. --- Measurement of car vibration in stationary condition --- p.71 / Chapter 6.2.2. --- Measurement of car vibration traveling in The Chinese University of Hong Kong (CUHK) --- p.72 / Chapter 6.2.3. --- Measurement of car vibration traveling in rough pattern road (Tai Po Road) --- p.73 / Chapter 6.3. --- Human motion analysis --- p.74 / Chapter Chapter 7 --- Conclusion --- p.76 / Reference --- p.78 / Appendix --- p.81

隨著工藝尺寸的縮小，集成電路的時序行為變得越來越難以預測，某原因在於各種偏差效應，比如製造偏差、供電電壓波動以及溫度變化。對於傳統的“確保正確“的設計方式，我們需要留出很大的餘量，這就減少了工藝進步帶來的好處。時序監測C Timing Speculation) 因為具有錯誤檢測和更正機制而成為一種很有前景的解決辦法。採用這種方式，電路可以工作在有不太頻繁時序錯誤的情況下。而對於這種時序監視的設計方式，現有的優化方法大多主要是在電路結構確定之後的一些小的改動。因為這些方法無法對電路結構進行改變，所以它們的效果很有限。因此，我們在這篇論文里提出了在電路綜合(synthesis)過程中的一些優化方法，這些方法是能夠改變電路結構的。我們提出的優化方法主要集中在優化電路的硬件開銷和電路性能的方面。我們提出的方法主要包括兩個設計階段。 / 第一個階段是在邏輯綜合(Logic synthesis) 的時候.在邏輯綜合的時候，我們有很大的自由度去根據時序監測的特性來改變電路的結構。如果結合了特殊的實現方法，電路出現時序錯誤的頻率就會得到降低，從而提高了電路的性能。 / 第二個階段是在邏輯綜合之後的后綜合(Post-synthesis) 階段。為了減少時序監測的硬件上的開銷，我們提出了基於retiming 手法的再綜合(resynthesis) 方法.這種方法可以減少可疑寄存器(suspicious FF) 的數量從而降低硬件開銷。另外這種辦法也可以提高電路的吞吐量(throughput) 。為了進一步對電路進行優化，我們挨著又提出了基於rewiring 手法的電路吞吐量優化方法。此外，利用這種方法我們還可以消除部份電路里的短通路(short path) 從而進一步減少電路的硬件開銷。在這個階段，我們仍然具有改變電路結構的靈活性，因此我們的方法具有很好的效果。 / With technology scaling, the timing behavior of integrated circuits (ICs) becomes more unpredictable due to various variation effects, such as manufacturing variability, voltage fluctuations and temperature changes. A large design guard band is therefore reserved to ensure “always correct“ operation for traditional designs, disminishing the benefits of technology scaling. Timing speculation with error detection and correction mechanisms is a promising solution to tackle the above problem. With this technique, circuit can work under infrequent timing errors. The existing optimization techniques for timing speculated circuits are mainly based on some small modifications after the circuit structure is determined. Without the ability to change circuit structure, the efficiency is limited. Therefore, in this thesis we propose optimization techniques during the process of synthesis so that the flexibility is provided to make circuit structural change. Our optimization fo¬cuses on hardware cost and circuit performance and the proposed techniques are included in two design steps. / First step is logic synthesis. During the process of logic synthesis, there is large flexibility to change the circuit structure by considering the features of timing speculation. With intentional strategy the timing error probability can be reduced so as to improve the circuit throughput. / Second step is post-synthesis techniques after logic synthesis. To reduce the hardware cost for timing speculation, we propose a re-synthesis method based on the idea of retiming to reduce the number of suspicious FFs where timing errors mainly happen. This technique can also help to improve the circuit throughput if carefully implemented. To further improve the throughput, we also propose to use rewiring technique which is also called redundancy addition and removal (RAR) to optimize circuit for throughput. Furthermore, this technique can also be used to break down short paths so as to save the hardware cost. During this step, flexibility is also provided to make circuit structural change so that the efficiency is guaranteed. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Liu, Yuxi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 70-76). / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Timing Speculation --- p.1 / Chapter 1.1.1 --- Circuit Timing Problem --- p.1 / Chapter 1.1.2 --- Possible Solution --- p.3 / Chapter 1.1.3 --- Timing Speculation is Promising --- p.4 / Chapter 1.1.4 --- Razor Flip-flop --- p.5 / Chapter 1.2 --- Problems for Timing Speculation --- p.6 / Chapter 1.2.1 --- Hardware Cost of Timing Speculation --- p.7 / Chapter 1.2.2 --- Performance of Timing Speculation --- p.8 / Chapter 1.3 --- Thesis Motivation and Organization --- p.9 / Chapter 1.4 --- Thesis Contributions --- p.11 / Chapter 2 --- Logic Synthesis for Timing Speculation --- p.13 / Chapter 2.1 --- Introduction --- p.13 / Chapter 2.2 --- Preliminaries --- p.14 / Chapter 2.2.1 --- Timing Speculation --- p.14 / Chapter 2.2.2 --- AIG-Based Logic Synthesis --- p.15 / Chapter 2.3 --- Logic Synthesis for Timing Speculation --- p.16 / Chapter 2.3.1 --- Proposed Optimization Metric --- p.17 / Chapter 2.3.2 --- Proposed Logic Synthesis Solution --- p.19 / Chapter 2.4 --- Experimental Results --- p.24 / Chapter 2.4.1 --- Experimental Setup --- p.24 / Chapter 2.4.2 --- Results and Discussion --- p.25 / Chapter 2.5 --- Conclusion --- p.30 / Chapter 3 --- Post-Synthesis Optimization for Timing Speculation --- p.31 / Chapter 3.1 --- Optimization for Timing Speculation by Retiming --- p.32 / Chapter 3.1.1 --- Introduction --- p.32 / Chapter 3.1.2 --- Preliminaries and Motivation --- p.33 / Chapter 3.1.3 --- Reducing Suspicious FFs by Retiming --- p.35 / Chapter 3.1.4 --- Reducing Timing Error Probability by Retiming --- p.41 / Chapter 3.1.5 --- Padding Short Paths --- p.43 / Chapter 3.2 --- Optimization for Timing Speculation by Rewiring --- p.47 / Chapter 3.2.1 --- Introduction --- p.47 / Chapter 3.2.2 --- Preliminaries --- p.48 / Chapter 3.2.3 --- Timing Optimization by Rewiring --- p.52 / Chapter 3.2.4 --- Reduce Hardware Cost by Rewiring --- p.60 / Chapter 3.3 --- Experimental Results --- p.62 / Chapter 3.4 --- Conclusion --- p.66 / Chapter 4 --- Conclusion --- p.68 / Bibliography --- p.76

最近社會對計算密集型應用程序和高性能的多核計算系統的研究興趣增加。隨著每片芯片和計算資源的核心數量不斷增長的趨勢，更好的金屬互連或其他替代是至關重要的。這亦要滿足高帶寬，低功耗，細小體積和高擴展性的要求。ITRS的報告指出，兼容CMOS的矽光子光互連是一種替代，它符合上述要求，包括體積細少和只需納秒的開關時間，所以矽微環諧振器是具潛能被用為2×2開關元件來建立大規模集成光互連。 / 然而，微環互連的可擴展性可能受限制的，其中四個關注點包括總功耗，插入損耗，光功率不均勻和總串擾。2×2切換微環需要一定的功耗，而插入損耗也限制了每條切換路徑所經過的開關元件的數量。換句話說，開關元件在交互/直行狀態下的非相等損失限制了光互連的可擴展性。此外，在考慮滿足大型光互連的要求，光功率的不均勻性是一個重要的問題。最後，在每個2×2開關元件，輸出光功率洩漏對大型的光互連的輸出造成許多可能的串擾。這在輸出端口的總串擾是十分嚴重，它會減少微環互連的可擴展性。因此，本論文的目的著重於降低整體功耗，路徑的總插入損耗，每個輸出端口的光功率不均勻和每個輸出端口的總串擾。 / 在這篇論文中，我們首先回顧微環諧振器的結構和微環互連的背景。限制互連的可擴展性也將被討論。然後，我們將回顧以前的研究，致力於解決可擴展性問題。通過利用微環開關元件的不相等特徵，我們提出一個有效的模型以找到最佳的開關配置，來減少總功耗和每通道的平均插入損耗。此外，我們還提出一個快速的算法，以較短的計算時間減少交叉狀態開關元件數量。 / There is an increasing research interest on networks-on-chip architectures for growing computation-intensive applications and high-performance multi-core computing systems recently. With the growing trend of number of cores per chip and computation resources per chip, the advancement for conventional interconnections is essential to meet the demands of high-bandwidth capacity, low power consumption, compact footprint and high scalability. A report from ITRS pointed out that optical interconnections based on Complementary Metal Oxide Semiconductor (CMOS)-compatible silicon photonics is an alternative to conform to the above requirements. The carrier-injection-based silicon microring resonators is a promising candidate to build large-scale-integrated optical interconnections using 2×2 switching elements due to its very compact footprint and potential sub-nanosecond switching time. / However, the scalability of microring-based interconnection is limited by issues including power consumption, insertion loss, nonuniformity and crosstalk. Current technology for a 2×2 switching elements of microring requires non-negligible power consumption at cross/bar states on average. Intrinsic insertion loss also limits the number of successive switching elements per switching path. In other words, asymmetric loss characteristics of switching elements limit the scalability of optical interconnections. Also, the nonuniformity of optical power is an important issue to be considered in meeting the requirement of a large-scale optical interconnection. Last, as in each 2×2 switching element, there is an optical power leakage to the non-intended output-port and thus it creates many possible crosstalk powers at each output-port. This total crosstalk at output is severe and needs to be reduced for the scalability consideration of microring-based interconnection. Hence, the aim of this thesis focuses on the reduction in overall power consumption, average total insertion loss per path, average nonuniformity of optical power and total crosstalk at each output-port. / In this thesis we firstly review the background of microring resonator architecture and microring-based interconnections. The severe asymmetric behaviors limiting the scalability of interconnection are discussed. Then we review previous work dedicated to the scalability issues. By leveraging the asymmetric characteristics at cross/bar states of microring switching elements, we then propose an efficient model to find the optimum switching configuration for minimizing the total power consumption and the average insertion loss per path. Heuristics is also proposed to minimize the number of cross state switching elements with a shorter computation time. The results depict that the optimum average total insertion loss per path using 2B-SE achieve a 3.65-dB improvement for 128×128 switch size. The optimum average total insertion loss using 2B-SE in the worst-cast path is shown to be 7.2 dB less than the baseline values without optimization. Furthermore, simulation results show that regarding the nonuniformity in the worst case of the worst case, with the optimum switching configuration, the best improvement is 9.6 dB; the average improvement is 8.7 dB and the least improvement is 7.2 dB for 128×128 switch size. On the other hand, for the total crosstalk per path, simulation results show that the optimum switching configuration can achieve a 1.87-dB improvement for 128×128 switch size on average, compared with the average case without optimization. Also, the total crosstalk has a 2.43-dB improvement for 128×128 switch size in the worst case. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Yuen, Piu Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 48-51). / Abstracts also in Chinese. / Acknowledgement --- p.i / Abstract --- p.ii / 摘要 --- p.iv / Table of Contents --- p.vi / Table of Figures --- p.viii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Overview of microring resonators and microring-based optical interconnection --- p.2 / Chapter 1.3 --- Asymmetric characteristics of microring switching elements --- p.3 / Chapter 1.4 --- Problem statement --- p.5 / Chapter 1.5 --- Motivation of this thesis --- p.6 / Chapter 1.6 --- Outline of this thesis --- p.7 / Chapter Chapter 2 --- Previous work on optimization of microring-based interconnection --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.2 --- A previous scheme for insertion loss reduction --- p.10 / Chapter 2.3 --- A previous scheme for nonuniformity reduction --- p.12 / Chapter 2.4 --- Prior work on power consumption in optical networks --- p.14 / Chapter 2.5 --- Prior work on crosstalk in optical cross-connect networks --- p.16 / Chapter 2.7 --- Summary --- p.17 / Chapter Chapter 3 --- Optimization scheme of microring-based interconnection configurations for reduction of power consumption and insertion loss --- p.19 / Chapter 3.1 --- Introduction --- p.19 / Chapter 3.2 --- Principle of determining the optimum switching configurations --- p.20 / Chapter 3.2.1 --- Calculations of power consumption and insertion loss --- p.23 / Chapter 3.3 --- Heuristic for reduction of power consumption and insertion loss --- p.24 / Chapter 3.4 --- Simulation results and discussion --- p.27 / Chapter 3.5 --- Summary --- p.32 / Chapter Chapter 4 --- Optimization scheme of microring-based interconnection configurations for the reduction of nonuniformity and crosstalk --- p.33 / Chapter 4.1 --- Introduction --- p.33 / Chapter 4.2 --- Principle of determining the optimum switching configurations --- p.34 / Chapter 4.2.1 --- Calculation of nonuniformity --- p.35 / Chapter 4.2.2 --- Calculation of crosstalk --- p.36 / Chapter 4.3 --- Simulation results and discussion --- p.39 / Chapter 4.4 --- Summary --- p.42 / Chapter Chapter 5 --- Conclusion and Future Work --- p.44 / Chapter 5.1 --- Conclusion of this thesis --- p.44 / Chapter 5.2 --- Future work --- p.46 / List of Publications --- p.47 / Bibliography --- p.48