In evaluating the BER for direct sequence spread spectrum multiple-access communication systems, it is very difficult to obtain a closed form expression for the output of these systems. Therefore one usually resort to simulation techniques such as the Monte Carlo method to evaluate the BER. The BER is usually small for these systems, hence an excessive amount of time and computations is required to adequately estimate the BER. One way to circumvent this problem is to utilize importance sampling method, which will give a good estimate for the BER with relatively small number of simulation runs. A technique known as quick simulation method developed from the principles of large deviation theory and importance sampling is used to estimate the BER. The quick simulation method is compared to two other methods used to evaluate the BER.

Performance analysis of optical heterodyne receivers in Wavelength Division Multiplexing (WDM) has been an important research area in the last few years. WDM can potentially provide hundreds of Gb/s channels in the same fiber. However, because of channel interference in WDM, performance analysis is important to design the system properly. In this thesis, a detailed noise and jitter analysis has been performed for an optical heterodyne PSK receiver used in WDM. In WDM, noise sources include shot noise, channel interference noise, and phase noise. These noise sources will not only add to the signal, but also cause timing jitter at the bit timing recovery. Expressions for the noise and jitter variances at the detector input are derived for both RZ and NRZ signals. Bit error probabilities as a function of WDM channel separation are computed. It is found that the overall bit error rate performance of RZ is better than NRZ.

A hardware system for investigating Intersymbol Interference (ISI) in an optical data storage system has been designed and constructed by the author. The system consists of a pattern generator which produces data patterns of variable lengths and bit rates to be recorded on the optical disk. Data marks of the readback signal are quantized by a light-speed clock-counter system, and transferred in parallel to a personal computer for analysis. SNR values for collected data are obtained by computing mark size deviations of the readback signal from the original marks. A pseudo-random pattern of 31 bits is used for calculating SNR values for different spot sizes. Finally, Additive Interleaving Detection (AID) technique is implemented to compute another set of SNR values. 3-5db SNR improvement is observed when AID technique is used.

Signal delay estimates for high-speed interconnection nets are formulated using analytical methods. The equations are suitable for estimating delay in interconnects of printed wiring boards and multi-chip modules where the resistance of wires is small. Effects of drivers, receivers, chip interfaces and wires on delay are considered by using simple models. The wires are treated as lossless transmission lines with capacitive discontinuities modeling receiver chip interfaces. Drivers are voltage sources with series resistance. Signal delay consists of line propagation delay and delay due to the change in rise time and reflections at the discontinuities. Various commonly used net topologies are identified and wiring rules and delay predictors provided for each of them. It is shown that interconnect delay can be formulated as a non-linear function of the product of the line characteristic impedance and load capacitance. SPICE simulations are sued to validate analytical derivations.

Since the profitability of VLSI industries is related to yield, the IC manufacturer finds it highly desirable to be able to predict the yield by computer-aided methods. A key part in the procedure to obtain yield by computer simulation is to find the critical area of a layout. This thesis is primarily devoted to the calculations of critical area. There are two techniques to find the critical area. In the first technique, an analytic method was used to analyze the circuit geometry in order to find the critical area. In the second technique a Monte Carlo Method is used. A program using this Monte Carlo yield simulation (the main method used in this thesis) has been developed for determining critical area of the metal layer of a 4K random access memory. The analytic method is used in a supporting way. The thesis also proposes an easy method to process the vast amount of layout database. This method reduces the time consumed by Monte Carlo simulation.

This MS thesis proposes a methodology to compute a frequency dependent current distribution for a ground plane with the ultimate aim of utilizing this current distribution to compute the plane parasitics. A iterative finite differencing technique is utilized to solve a two dimensional diffusion equation for the current distribution on the plane. Starting with an initial DC current density over the entire plane grid, the frequency dependent current density is obtained by imposing the necessary boundary conditions and allowing the current to redistribute itself over the plane. An iterative procedure based on simultaneous over relaxation is employed to get faster convergence. This method takes into account the presence of sources, sinks and holes on the plane. Finally the plane parasitics are computed using integral methods and energy considerations.

The effects of high field stress on interface trap densities (Dit in MOS transistors are compared using three methods: charge-pumping, subthreshold swing and 1/f noise. The experimental MOS devices subjected to high field stress originated from two wafer lots processed with different concentrations of copper in the buffered oxide etchant. For the charge-pumping and subthreshold methods, no dependency is found on stress current polarity, wafer lot or transistor type (n- or p-channel). These two methods yield similar Dit values. For the 1/f noise method, no dependency is found on current polarity or wafer lot. However, the noise in the n-channel devices increases by several orders of magnitude as compared to the p-channel devices. A large discrepancy is found between Dit calculated from 1/f noise when compared to charge-pumping/subthreshold swing results for n-channel transistors. For p-channel transistors, the 1/f Dit results are in much better agreement with the results of the other two methods.

Three metal compositions are patterned via plasma etching into comb structures. The comb structures have pitches of 4 μm, 5 μm, 7 μm and 12 μm, with a line width of 2 μm, on a field oxide of 8,000 Angstroms thickness, using <111> p-type substrates. These comb test structures have been used to determine the number of bridges, and thus the yield, of the metal compositions: pure aluminum, silicon(2%)-aluminum, and copper(0.5%)-silicon(2%)-aluminum. Bridge failures are photographed and classified according to the source of the defect. The defects due to plasma particles are used to determine a yield model for this etch process. Through the use of yield model and test structure data the etch process is evaluated for the different metal systems. This allows a quantitative comparison of the systems in terms of defect clustering, defect density and defect size distribution, and hence projections for the best yielding process via the yield model.

In this thesis, a computer simulation has been done to evaluate the wavelength chirping and pulse broadening effects induced by the direct intensity modulation using Distributed Feedback (DFB) laser diodes. In the simulation, a DFB laser diode is driven by either square wave current pulses or pulses with a small current Step in the Leading Edge (SLE). A comparative study is performed to justify the effectiveness of using SLE waves in modulation to reduce wavelength chirping and pulse broadening. Numerical results from the single-mode rate equations show that the SLE wave modulation reduces the wavelength chirping and pulse broadening by a factor of 2. The optimal SLE pulse has a prepulse duration of 0.15 ns and a prepulse current level of 70.0 mA.

Output impedance matching for transmission line drivers is not easy to implement due to unavoidable process tolerances. An automatic system for adjusting the output impedance of fast CMOS drivers, on one chip, is described. The output impedance of all identical drivers is adjusted to match the impedance at the input of a reference transmission line, equal in geometry to the lines connected to the other drivers, by a circuit for measuring and correcting the mismatch between the output impedance of one of the drivers, taken as reference and dedicated for this purpose. The voltage measured at the far end of the reference line is sent to a differential amplifier where it is compared with the supply voltage of the final driving stage. According to the comparison result at specific time intervals, a signal is supplied to the regulator which supplies power to the penultimate driving stage, thereby controlling the resistance of the driver to match the line impedance. Simulations have shown that the percentage deviations of the far-end line voltage is approximately 3% for this design compared to a system without feedback which has a far-end line voltage deviation of approximately 18%.