Arthur Dickson Hause. / "August 25, 1960." Issued also as a thesis, M.I.T. Dept. of Electrical Engineering, August 22, 1960. / Bibliography: p.48-49. / Army Signal Corps Contract DA36-039-sc-78108. Dept. of the Army Task 3-99-20-001 and Project 3-99-00-000.

Thomas Kailath. / "May 25, 1959." Based on a thesis, M.I.T. Dept. of Electrical Engineering, May 25, 1959. / Bibliography: p. 46-47. / Army Signal Corps Contract DA36-039-sc-78108. Dept. of the Army Task 3-99-20-001 and Project s 3-99-00-000.

Elie J. Baghdady. / "July 30, 1957." / Bibliography: p. 48. / U.S. Army Signal Corps Contract No. DA36-039-sc-64637 Dept. of the Army Task 3-99-06-108 Project 3-99-00-100

Thesis (Ph. D.)--University of Washington, 1984. / Vita. Bibliography: leaves [335]-348.

Thesis (Ph. D.)--University of Nevada, Reno, 2005. / "December 2005." Includes bibliographical references (leaves 213-220). Online version available on the World Wide Web. Library also has microfilm. Ann Arbor, Mich. : ProQuest Information and Learning Company, [2005]. 1 microfilm reel ; 35 mm.

A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal delay time, chip area and I/O pins. The coefficients of the filter can be updated serially in real time for time invariant and adaptive filtering. A fourth order bit/serial IIR filter is implemented on a 2 micron CMOS technology clocked at 55 MHz. / Graduation date: 1992

Clock-feedthrough effects, channel-length modulation and device mismatch are the main causes of the inaccuracy of Switched-Current (SI) circuits. In this paper, these non-ideal effects are analyzed. A high-performance current mirror, namely regulated cascode current mirror, which eliminates drain voltage variation problem is introduced. By using this current mirror as a basic memory cell, a clock-feedthrough cancellation circuit is developed, which ideally solves the clock-feedthrough and drain voltage variation problems. A fifth-order SI lowpass Chebyshev ladder filter is built using the proposed cancellation circuit and implemented in a two-micron P-well standard digital CMOS process by MOSIS. Another emerging technique, dynamic current mirrors or current copiers, is introduced. Improved dynamic current mirror cell and dynamic current mirror-based integrators have been developed. / Graduation date: 1992

The design and implementation of Switched-Current (SI) ladder filters is described. SI filters require only a standard digital CMOS process and the power supply voltage requirement is low. SI circuits also can be potentially operated at higher frequencies than Switched-Capacitor (SC) filters due to the low-impedance wideband nodes of the current mirrors. A simple method has been developed to design SI ladder and biquadratic fllters with maximum dynamic range that leverages the well-established design methodologies of SC filters. A standard digital 2-micron n-well CMOS process has been used to implement two high-order ladder filters and two biquadratic filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to the switched-capacitor technique. Analysis of the factors that effect dynamic range in SI filters is presented. The factors that contribute to harmonic distortion in the current-mode circuits are characterized and the relationships to maximum signal size are established. Using measurements of the input-referred noise from SI filters, the dynamic range is obtained. / Graduation date: 1991

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004. / Includes bibliographical references (leaves 108-111). Also available in electronic version. Access restricted to campus users.

Thesis--Ph. D., University of Hong Kong, 1981.