With the increased attention on high efficiency and energy savings, power electronic energy conversion equipment is increasingly incorporated in all levels of the power system. The drawback of such equipment is the generation of nonsinusoidal currents in the power distribution network due to the nonlinear operation. Harmonic currents may distort the line voltages and lead to several unwanted effects including equipment overheating, system failure, interference with communication systems, etc. In response to these concerns, this research presents an active filter for the cancellation of harmonic line current distortion. The active filter used in this research is connected in parallel with the nonlinear load and is designed for a three-phase three-wire industrial power system. The filter consists of a voltage source inverter connected through a coupling inductor to the terminals of the ac-source. The inverter is controlled via a space vector-pulse width modulation (SVPWM) algorithm that is generated using a digital signal processor (DSP). In order to reduce the distortion resulting from the switching nature of the active filter inverter, a switching ripple filter is connected in parallel. The control algorithm of the active filter is based on the rotating reference frame theory. For each harmonic which is to be cancelled, a corresponding synchronous reference frame is generated to extract the harmonic phase and magnitude. With this information, each harmonic current component can be separately controlled and the proposed algorithm can therefore compensate for hardware effects such as measuring delays and component transfer functions. For the extraction of the harmonic components, a finite impulse response filter is used in order to quickly react to changing load currents. An adapting algorithm is implemented to compensate for slowly varying system parameters. Simulations under varying load and transient conditions are performed. The results show nearly perfect cancellation performance for the proposed active filter control algorithm. / Graduation date: 2001

Yeung Nang Ching. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 72-74). / Abstracts in English and Chinese. / ACKNOWLEDGMENTS --- p.I / ABSTRACT --- p.II / 摘要 --- p.III / TABLE OF CONTENTS --- p.IV / LIST OF FIGURES --- p.VII / LIST OF TABLES --- p.X / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Overview of filter --- p.1 / Chapter 1.1.1 --- History --- p.1 / Chapter 1.1.2 --- Application of analog filter --- p.2 / Chapter 1.1.3 --- Category of continuous time filters --- p.3 / Chapter 1.1.4 --- Problem issued from Active RC filter --- p.7 / Chapter 1.2 --- Motivation --- p.7 / Chapter 1.3 --- Outline --- p.8 / Chapter CHAPTER 2 --- FILTER FUNDAMENTAL --- p.9 / Chapter 2.1 --- Overview --- p.9 / Chapter 2.2 --- Terminology --- p.9 / Chapter 2.3 --- General Goals of Filter Design --- p.11 / Chapter 2.4 --- Standard Lowpass Filter Characteristic --- p.11 / Chapter 2.4.1 --- Butterworth --- p.11 / Chapter 2.4.2 --- Chebyshev --- p.12 / Chapter 2.4.3 --- Elliptic-Function --- p.13 / Chapter 2.5 --- Study on Different Tuning Approaches --- p.13 / Chapter CHAPTER 3 --- CURRENT DIVISION NETWORK (CDN) --- p.18 / Chapter 3.1 --- Overview of Current Division Technique --- p.18 / Chapter 3.2 --- Second Order Effects --- p.23 / Chapter 3.3 --- Working Principle of CDN --- p.23 / Chapter 3.4 --- Performances of CDN --- p.25 / Chapter 3.4.1 --- General Properties of CDN --- p.25 / Chapter 3.4.2 --- Input Resistances of CDN --- p.26 / Chapter 3.4.3 --- Noise Performance of CDN --- p.27 / Chapter CHAPTER 4 --- REALIZATION OF THE FILTER --- p.31 / Chapter 4.1 --- Overview --- p.31 / Chapter 4.2 --- Traditional Kerwin Huelsman Newcomb (KHN) Biquad --- p.31 / Chapter 4.2.1 --- State Variable Method --- p.31 / Chapter 4.2.2 --- KHN Biquad --- p.32 / Chapter 4.3 --- Proposed Filter --- p.33 / Chapter 4.3.1 --- Biquad with CDN --- p.33 / Chapter 4.3.2 --- A dvantages of Proposed Filter --- p.36 / Chapter 4.3.3 --- Schematic of Proposed Filter --- p.38 / Chapter CHAPTER 5 --- LAYOUT CONSIDERATION --- p.41 / Chapter 5.1 --- Overview --- p.41 / Chapter 5.2 --- Process Information --- p.41 / Chapter 5.3 --- Transistor Layout Techniques --- p.42 / Chapter 5.3.1 --- Multi-finger Layout Technique --- p.42 / Chapter 5.3.2 --- Common-Centroid Structure --- p.43 / Chapter 5.3.3 --- Guard Ring --- p.45 / Chapter 5.4 --- Passive Element Layout Techniques --- p.45 / Chapter 5.5 --- Layout of Whole Design --- p.47 / Chapter CHAPTER 6 --- SIMULATION RESULT --- p.49 / Chapter 6.1 --- Operational Amplifier --- p.49 / Chapter 6.2 --- Overall Performance of filter --- p.55 / Chapter CHAPTER 7 --- MEASUREMENT RESULT --- p.60 / Chapter 7.1 --- Measurement Setup --- p.60 / Chapter 7.2 --- Time Domain Measurement --- p.62 / Chapter 7.3 --- Frequency Domain Measurement --- p.63 / Chapter 7.4 --- Measurement of Non-Linearity --- p.66 / Chapter 7.5 --- Summary of the Performance --- p.69 / Chapter 7.6 --- Comparison on Tuning Ability --- p.70 / Chapter CHAPTER 8 --- CONCLUSION --- p.71 / BIBLIOGRAPHY --- p.72

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University of Macau / Faculty of Science and Technology / Department of Electrical and Computer Engineering

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No description available.

Este trabalho apresenta uma abordagem paralela em FPGA para implementação de controladores digitais, com a finalidade de reduzir o tempo computacional de execução das leis de controle. A técnica de controle utilizada na implementação proposta pode ser aplicada para a compensação seletiva de harmônicos em filtros ativos de potência (FAP). Para compensar mesmo um número reduzido de harmônicas são necessárias múltiplas instruções de cálculo, envolvendo multiplicações e adições. Desta forma, para melhorar o desempenho computacional do sistema, é proposta uma estrutura paralela para implementação do controlador. Para compensação de um número maior de harmônicas é realizada a decomposição das tensões em suas componentes harmônicas em eixos síncronos utilizando a Transformada Discreta de Fourier. Esta estratégia permite um tempo de cálculo fixo independente do número de harmônicas, até o limite imposto pela frequência de amostragem. Os resultados experimentais são apresentados para comparar o tempo de execução da abordagem paralela proposta com o tempo de execução sequencial convencionalmente utilizado na literatura. / This paper presents a parallel approach to FPGA implementation of digital controllers, in order to reduce the computational time for implementing the control laws. The control technique used in the proposed implementation can be applied for selective harmonic compensation in active power filters (APF). To compensate for even a small number of harmonics requires multiple calculation instructions involving multiplications and additions. Thus, to improve the performance of the computer system is proposed to implement a parallel structure of the controller. To compensate for a larger number of harmonics is performed in the decomposition voltages of the harmonic components into their frames synchronous using the Discrete Fourier Transform. This strategy allows a calculation time fixed regardless of the number of harmonics up to the limit imposed by the sampling frequency. The experimental results are presented to compare the runtime of the proposed parallel approach with the sequential execution time conventionally used in the literature.

No description available.

Thesis (Ph.D.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

University of Macau / Faculty of Science and Technology / Department of Electrical and Computer Engineering