published_or_final_version / Electrical Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / abstract / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Thesis (Ph. D.)--University of Hong Kong, 1988.

Thesis (Ph. D.)--University of Hong Kong, 2007. / Title proper from title frame. Also available in printed format.

Power quality has become an important concern to both electric utilities and end users due to the increased use of non-linear loads in modem power systems over the past decade. Nonlinear loads inject harmonics into the power system and thus may lead to poor power quality and lower power factor. Current and voltage harmonics can adversely affect the operation of sensitive devices. A common remedial solution to reduce the effects of harmonic distortion in a power system is filtering. Passive and active filters are two common types of harmonic filters. An active filter, in general, is a controllable current source that injects current at the same magnitude and opposite phase to that of the harmonic current. For this thesis work, a DSP-controlled active filter to cancel lower order (5th, 7th, 11th, and 13th) harmonics in a three-phase, three-wire power system is designed. The proposed active filter employs a series LC tank tuned to a high frequency, along with a pulse-width modulated (PWM) converter topology. The PWM control of the active filter is implemented in a TMS320F240 DSP. The DSP implementation enhances the performance of the filter in real-time and enables the filter to compensate for varying loads. Additionally, the use of DSP-control reduces the number of components and therefore reduces the cost and improves the reliability of the overall system. The uniqueness of the filter is in its ability to control each harmonic separately. A laboratory prototype of the proposed active filter has been built and tested to verify the performance of the active filter. / Graduation date: 2001

The objective of this thesis is to design a high speed digital FIR filter. The inputs of the system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which are unweighted single-bit binary numbers at 156MHz, multiply each bit with the corresponding coefficient and add them to get a weighted multi-bit output at 20MHz. / Graduation date: 1997

Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends on many factors such as sensitivity to finite word-length quantization effects, hardware complexity and power consumption. The objective of this thesis is to examine digital IIR (Infinite Impulse Response) filter structures for the VLSI implementation of narrow-band sharp-transition filters. This thesis examines several different digital IIR filter structures; namely cascade form IIR filter, five different digital lattice filters and lattice wave digital filter structures. For fixed-point implementation, the sensitivity, round-off noise properties and the scaling of these filter structures are described and analyzed. These filter structures are compared with respect to the architectural complexity, the sensitivity to coefficient quantization, the round-off noise due to product quantization and the signal dynamic range. Fixed-point implementation simulations using two's-complement arithmetic are carried out for a number of narrow-band sharp-transition digital low-pass filters. / Graduation date: 1995

Thesis (M. Phil.)--University of Hong Kong, 1988.

Thesis (M. Phil.)--University of Hong Kong, 1989.