The objective of this thesis is to design a high speed digital FIR filter. The inputs of the system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which are unweighted single-bit binary numbers at 156MHz, multiply each bit with the corresponding coefficient and add them to get a weighted multi-bit output at 20MHz. / Graduation date: 1997

Due to advances in high-density low-cost VLSI and communication technology, digital filtering and signal processing are being widely used for real-time signal processing applications. Given the filter specification, choosing the best filter structure for a given application is not a trivial task. The choice of a particular filter structure depends on many factors such as sensitivity to finite word-length quantization effects, hardware complexity and power consumption. The objective of this thesis is to examine digital IIR (Infinite Impulse Response) filter structures for the VLSI implementation of narrow-band sharp-transition filters. This thesis examines several different digital IIR filter structures; namely cascade form IIR filter, five different digital lattice filters and lattice wave digital filter structures. For fixed-point implementation, the sensitivity, round-off noise properties and the scaling of these filter structures are described and analyzed. These filter structures are compared with respect to the architectural complexity, the sensitivity to coefficient quantization, the round-off noise due to product quantization and the signal dynamic range. Fixed-point implementation simulations using two's-complement arithmetic are carried out for a number of narrow-band sharp-transition digital low-pass filters. / Graduation date: 1995

A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal delay time, chip area and I/O pins. The coefficients of the filter can be updated serially in real time for time invariant and adaptive filtering. A fourth order bit/serial IIR filter is implemented on a 2 micron CMOS technology clocked at 55 MHz. / Graduation date: 1992

No description available.

Graduation date: 1995

A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed to implement the digital section of mixed-signal IC applications. This FSCL circuit technique offers the advantage of low overlap current spikes during the switching transitions of conventional CMOS gates. This overlap current spike has become one of the major obstacles in improving the accuracy and performance of mixed-signal IC applications. Using simple circuits, FSCL logic family can be interfaced with the existing CMOS family. Thus it can nearly eliminate the power noise issue in the mixed-signal IC design. In this thesis, design of a sinc3 decimation filter using the FSCL technique for a 2nd order delta-sigma modulator has been presented. Simulation results show that this particular decimation filter, using the newly developed FSCL technique, improves the performance of the mixed-signal system. / Graduation date: 1994

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

Moving-average matched filters (MAMF's) are a class of digital filters used to detect the presence of a known signal in noise. Designing matched filters requires knowledge of the structure of the signal and the noise. If the spectral density of the noise is not known or is changing with time its spectral characteristics must be estimated. Since spectral estimators derive their estimates from a random process realization, the estimates themselves are probabilistic in nature. The performance of MAMF's based on these estimates must, in turn, be distributed in a probabilistic sense. This thesis investigates the performance of MAMF's designed on the basis of several different spectral estimators. Theoretical aspects of MAMF's and spectral estimators are reviewed and developed. A simulation system is used to exercise the spectral estimators and MAMF's and to provide comparative performance data. A graphical representation, using contour plots, is developed and can be used to predict the performance of a given MAMF/signal/spectral estimator combination. Finally, several methods of generating MAMF's whose output performance is relatively insensitive (or robust) to the probabilistic variations caused by the spectral estimators are developed and evaluated. The latter incorporates knowledge of the empirical distribution of the particular spectral estimator used, as well as the freedom of manipulating the signal. / M.S.