Model based approach for design and analysis of systems has made great advances in the last decade. Model driven system development methodologies like model integrated computing (MIC) allow integration and manipulation of models with manageable complexity in various aspects of system design. Model based approach is used in embedded system design and analysis in order to integrate efforts in system specification, design, synthesis, validation, verification and design evolution. Mathematical models like hybrid automaton are used for analysis of embedded systems, which have tightly coupled discrete and continuous components. In order to perform design and analysis for hybrid systems, various approaches have been developed to explore hybrid state space. However, model checking algorithms designed using these state exploration techniques are constrained with the implementation details of the computation tools and that limits the creation of algorithms for some specific design and analysis purposes. This thesis presents a metamodel based language and a computation platform for designing hybrid system models and designing analysis algorithms as models that are generic and implementation independent. The metamodel based modeling language provides well-defined abstract concepts such as continuous state sets, operators for reachability computation, and Boolean operations on state sets. This language uses multiple aspects to separate the concerns of analysis algorithms into programming logic, system models, and related data. On one hand, the models of analysis algorithms are abstract and therefore the design of algorithms can be made independent of implementation details. On the other hand, translators are provided to automatically generate implementations from the models for computing analysis results based on computation kernels, which have been created by enriching the capabilities of existing computation tools such as d/dt and Level Set toolbox. This platform forms an integral part of a prospective integrated suite of tools that would be used in every step of model based design of embedded systems all the way from specification to production.

Middleware is increasingly being used to develop and deploy large-scale distributed real-time and embedded (DRE) systems in domains ranging from avionics to industrial process control and financial services. Applications in these DRE systems require various levels and types of quality of service (QoS) from the middleware, and often run on heterogeneous hardware, network, OS, and compiler platforms. To support a wide range of DRE systems with diverse QoS needs, middleware often provides many (i.e., 10s-100s) of options and configuration parameters that enable it to be customized and tuned for different use cases. Supporting this level of flexibility, however, can significantly complicate middleware and hence application QoS. This problem is exacerbated for developers of DRE systems, who must understand precisely how various configuration options affect system performance on their target platforms. This thesis provides two contributions to R&D on model-driven development (MDD) techniques that help codify the impact of middleware configurations on endto- end distributed real-time and embedded (DRE) system quality of service (QoS). First, we describe how MDD techniques can help select middleware configuration parameters that satisfy key functional and QoS requirements of DRE systems. Second, we apply our MDD techniques to empirically evaluate the end-to-end QoS of representative DRE systems in the avionics and industrial manufacturing domains. Our results show how MDD techniques significantly enhance conventional ad hoc processes used by developers to configure middleware that meets the QoS needs of DRE systems.

The creation of a memory system based on that of humans is detailed for a cognitive robot. Three types of memory systems are outlined and implemented within the framework of the cognitive system being implemented for ISAC, a humanoid robot. These three memory types are those attributed to humans in psychology. These memory systems include a Procedural Memory to allow ISAC to store and retrieve movement behaviors, a Semantic Memory to represent semantic facts in a consistent manner throughout the cognitive system, and an Episodic Memory system to record the state of ISAC's cognitive system through task execution and allow for learning from past episodes. A retrieval technique was developed for the EM system that allowed for the inclusion of several factors important for retrieval of the correct memory into the Episodic Working Memory. The importance of these factors was demonstrated, and the performance of the system was compared with the more traditionally minded method of storing all experiences for future retrieval. It is shown how the decay of memories allows for performance gains in a more domain-specific search. The three systems were implemented, and an adaptive working memory system was created for each. Several tools were developed to aid in memory creation and testing as well as cognitive system debugging, and a sample perceptual agent was created to show how the Semantic Memory can interoperate with perception.

With ever decreasing device feature sizes, subsequent generations of semiconductor logic circuits are more vulnerable to ionizing radiation effects when compared to their predecessors. Single Event Upsets (SEUs) and Single Event Transients (SETs) induced in Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) are a major concern for designers. In an ASIC, a single event strike can corrupt the data being processed, whereas in a FPGA, a single event strike can induce both data and functionality errors. Traditional radiation hardening techniques for ASICs and FPGAs aim to harden the circuit as a whole. Techniques like Triple Mode Redundancy (TMR), temporal redundancy, scrubbing, and reconfiguration involve significant penalties (sometimes greater than 3X). In commercial and non-critical applications, a 3X penalty cannot be tolerated. Further, most of the commercial and non-critical applications may not require a fully hardened implementation. In this thesis alternative soft error mitigation techniques are presented which improve reliability while minimizing penalties in area and performance. Part I of the thesis deals with soft error mitigation in ASICs. A two-level (VHDL and SPICE) simulation methodology is used to identify sensitive cells in a 4-bit Arithmetic and Logic Unit (ALU). A selective hardening approach is used to harden the ALU by targeting only the most sensitive cells. Trade-offs between reliability and area penalty are presented. Part II of the thesis discusses soft error mitigation in FPGAs. A 16-bit single instruction issue processor is designed with Error Detection and Correction (EDAC). Two different error detection codes (Berger Check Prediction and Remainder and Parity Check) are compared against TMR. Area and performance results of the EDAC techniques are presented.

Energy deposition from particles in space can cause upsets in microelectronic devices resulting in unreliable systems. A Geant4 based application, MRED (Monte Carlo Radiative Energy Deposition), is used to investigate energy deposition in scaled microelectronic structures. Simulations in this work show that neglecting the ion-ion interaction processes (both particles having Z > 1) results in an underestimation of the total on-orbit single event upset (SEU) error rate by more than two orders of magnitude for certain technologies. The inclusion of ion-ion nuclear reactions leads to dramatically different SEU error rates for modeled CMOS devices containing high Z materials compared with direct ionization by the primary ion alone. Device geometry and material composition have a dramatic effect on charge generation in small sensitive volumes for the spectrum of ion energies found in space, compared with the limited range of energies typical of ground tests. Comparisons between MRED results and previously published results from another Monte Carlo based code are shown to have good agreement.

It is now well known to the radiation effects community that single event effects caused by energetic particles, particularly single event transients, will be among the dominant reliability issues in advanced integrated circuits. A single event upset is a static error in storage elements such as memory and is independent of clock frequency. Whereas single event transients are glitches that propagate through combinational logic elements and get stored as incorrect data. Such errors are dependent on both the clock frequency and the pulse width of the transient. Precise knowledge of particle-induced transient pulse widths is important to develop hardening techniques to mitigate the effects of these transients. However there have not been many efforts in the past to characterize these transients, primarily because they did not pose a great threat to reliability and/or did not contribute significantly to error rates in older technology devices. Also it has been very difficult to measure these transients accurately, as they occur on pico-second time scales. However, with decreasing feature sizes and increasing clock speeds, single event transients have already started to dominate soft error rates. This thesis presents a novel circuit technique to measure single event transients accurately. Laser test results are presented to validate this approach.

Low voltage differential signaling (LVDS) is becoming increasingly common in systems where high-speed, low-power data transfer across physical layer interfaces is required. In this work, the heavy ion and dose rate radiation response of a LVDS driver and receiver is evaluated and understood though various simulation techniques. A novel database approach to heavy ion simulations is introduced which effectively models the charge collection with respect to linear energy transfer (LET), time, circuit bias and strike location at 85 different locations in the circuit. Sensitive areas for each transistor in the circuit and single-event cross sections are recorded for several different test conditions. A dose rate simulation methodology is used which utilizes photocurrent models calibrated to previous test data of the semiconductor process used in the LVDS device fabrication. Dose rate simulations evaluate the circuit photocurrents as well as dose rate induced phenomena such as pushout, jitter, glitch upset and recovery time.

The focus of this work was the development of equipment and image processing techniques to observe the melting characteristics at the leading edge of a gas tungsten arc weld. A high speed digital imaging system, along with a macro lens imaging system, were used to obtain high quality images of the weld pool motion in a digital format for computer processing. Once in the computer, a LabVIEW viewer program was used to view the images at various speeds. These images were further enhanced to bring out the leading edge of the weld. Various image processing techniques, including filtering and convolution, were used. Once the proper images were obtained, the Fast Fourier Transform and other techniques were used for the analysis of these images.

The procedure currently used for cochlear implementation can be improved with the aid of techniques developed in medical imaging. A suitable path accessing the cochlea can be determined before the operation by locating a point in the facial recess and another point in the basal turn of the cochlear on the CT image of the patients ear. Outlines of those two structures are drawn by a qualified surgeon creating an atlas that is used to identify the same structures in the patients ears. By registering the atlas image to the patient image and tracking the deformations applied to the labeled voxels in the atlas, the location of those structures can be determined. A 12 parameter affine registration is performed first using mutual information as a similarity measure. After that a non rigid registration algorithm (Adaptive Bases Algorithm) is applied to register the ear in the atlas to the patients ear. The structures outlined in the atlas are deformed using the computed transformations and the resulting intensity centroids are used to draw the required safe path. The developed algorithm succeeded in finding a suitable path in all of the nine ears it was tested on.

This dissertation proposes a novel approach, applicable in the design-time analysis and verification of computer-based systems. The proposed approach, platform modeling, constructs analysis models capturing the system's behavior on a particular implementation platform. The approach is discussed in the context of Model-Integrated Computing, which is a development methodology leveraging on the use of domain-specific modeling languages and advanced model transformation techniques. During development, platform-independent design models are refined into platform-specific models using model transformation. The main contribution of this work is the enhancement of this process with the automatic generation of analysis models. These analysis models assign platform-specific semantics to the design model. This assignment is done through a transformational approach, using graph transformation. The dissertation presents a case study using a conventional graph transformation tool. Then, a new graph transformation language designed specifically for such transformations is proposed, and its advantages are demonstrated.