Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures such as DRAMs. DRAMs are built using minimized transistors with presumably uniform speed in an organized array structure. Process variation can introduce latency disparity among different memory arrays. With the proliferation of 3D stacking technology, DRAMs become a favorable choice for stacking on top of a multi-core processor as a last level cache for large capacity, high bandwidth, and low power. Hence, variations in bank speed create a unique problem of non-uniform cache accesses in the 3D space. In this thesis, we investigate cache management techniques for tolerating process variation in a 3D DRAM stacked onto a multi-core processor. We modeled the process variation in a 4-layer DRAM memory to characterize the latency variations among different banks. As a result, the notion of fast and slow banks from the core's standpoint is no longer associated with their physical distances with the banks. They are determined by the different bank latencies due to process variation. We develop cache migration schemes that utilize fast banks while limiting the cost due to migration. Our experiments show that there is a great performance benefit in exploiting fast memory banks through migration. On average, a variation-aware management can improve the performance of a workload over the baseline (where the speed of the slowest bank is assumed for all banks) by 17.8%. We are also only 0.45% away in performance from an ideal memory where no PV is present.

This experiment examined the effect of time delays on the ability to stabilize an inverted pendulum. The results were determined by examining the amount of time the systems oscillations remained bounded before increasing exponentially. This was done for each combination of time delay and pendulum length covered in this experiment. The results showed that for a pendulum length of 49 meters, all time delays in the identified range were able to be stabilized. The results also showed that for a pendulum length of 2.45 meters, no time delays in the identified range were able to be stabilized.

To date cardiovascular diseases (CVD) account for approximately 35% of all deaths worldwide. Many of these deaths are preventable if the risk of developing them can be accurately assessed early. Medical devices in use today cannot determine a patients risk of developing a CVD condition. If accurate risk assessment was readily available to doctors, they can track rising trends in risk levels and recommend preventative measures for their patients. If patients had this risk assessment information before symptoms developed or life-threatening conditions occurred, they can contact their doctors to inquire about recommendations or seek help in emergency situations. This thesis research proposes the idea of using evolutionary programmed and tuned fuzzy logic controllers to diagnose a patients risk of developing a CVD condition. The specific aim of this research seeks to advance the flexibility and functionality of fuzzy logic systems without sacrificing high speed and low resource utilization. The proposed system can be broken down into two layers. The bottom layer contains the controller that implements the fuzzy logic model and calculates the patients risk of developing a CVD. The controller is designed in a context switchable hardware architecture the can be reconfigured to assess the risk of different CVD diseases. The top layer implements the evolutionary genetic algorithm in software, which configures the fuzzy parameters that optimize the behavior of the controller. The current implementation inputs patients personal data such as electrocardiogram (ECG) wave features, age and body mass index (BMI) and outputs a risk percentage for Sinus Bradycardia (SB), a common cardiac arrhythmia. We validated this system via Matlab and Modelsim simulations and built the first prototype on a Xilinx Virtex-5 FPGA platform. Experimental results show that this 3-input-1-output fuzzy controller with 5 fuzzy sets per variable and 125 rule propositions produces results within an interval of approximately 1us while reducing hardware resource utilization by at least 25% when compared with existing designs.

As the search for fabrication techniques towards the production of large area defect free three-dimensional photonic crystals continues, holographic lithography presents itself as a possible solution. In this thesis, a simplified method that is free of complex optical setups is demonstrated. Within the core of the method presented lies a readily available optical component, a phase grating that by design presents a region of interference available for lithographic processing. The phase grating exhibiting a one-dimensional periodic arrangement designed to diffract into three substantial orders necessitates two exposures after which a three-dimensional periodic arrangement is realized. The negative tone photo resist, SU-8 utilized to record the designed intensity distribution proves itself as a viable intermediary towards high dielectric contrast structures. The previously established large bandgap photonic crystals present fabrication challenges and thus approximations to these structures have been proposed. The specific method employed opens the door to only one of the previously established champion photonic crystals but nevertheless the most sought after diamond structure predicted to exhibit one of the largest possible band gaps. The woodpile structure possessing some of the qualities of the diamond lattice is proven to be an adequate practical approximation and once properly designed exhibit large band gaps. The specific technique employed permits the exploration of the 11 FCC space groups along with the FCT and Tetragonal space groups. The fascination that these structures have provoked is fueled by the vast predicted applications encompassing nearly all known scientific disciplines. One does not have to venture far to realize the potential held for the telecommunication industry such as dense wavelength multiplexers, high efficiency lasers, lasers of previously unavailable wavelengths, super continuum sources, flat lenses, superprisms, lossless waveguides, and resonant cavities to mention a few. Developments of these devices would progress the advancement of technologies such as optical storage, drug delivery systems, and advanced imaging. Some have even compared the discovery of these materials to the revolution achieved by the semiconductor industry with the advent of controllable electronic band gaps.

Two significant problems are present which impede the widespread utilization of many implantable devices with great potential: 1) the lack of availability of an efficient energy source suitable for long-term operation, and 2) the lack of a robust, low-power communication path which does not rely on wired connectivity. The creation of a feasible solution to these two power and communication issues is critical to the success of many future implantable devices. This foundational work details the development of a general solution for the above issues, in a power and communications platform technology for implantable devices. The platform is developed based on the volume conduction technology explored in our laboratory. Ultimate devices are small in size, with the incorporation of a rechargeable battery and electrodes used for interfacing with external components through the skin. An external patch, or "energy pad," containing low-profile electrodes and circuitry, is used as the external interface for recharging and communicating with implanted devices. System design focuses on reliability and ease of integration into a variety of implantable systems, making them feasible for clinical application. Because this is the first system that uses volume conduction for both power and communication purposes, a novel "X-Δ model" of the system is created for use in analyzing the energy transfer of such systems to assist in engineering design. The model, which incorporates components to represent actual current pathways in the skin, is also used in finding theoretical maximum limits of volume conduction energy transfer efficiency for specific skin-electrode setups, proving the technology as a viable option for practical implanted devices.

Artificial neural networks (ANN) offer tremendous promise in classifying electrocardiogram (ECG) for detection and diagnosis of cardiovascular diseases. In this thesis, we propose a reusable neuron architecture (RNA) to enable an efficient and cost-effective ANN-based ECG processing by multiplexing the same physical neurons for both feed-forward and back-propagation stages. RNA further conserves the area and resources of the chip and reduces power dissipation by coalescing different layers of the neural network into a single layer. Moreover, the microarchitecture of each RNA neuron has been optimized to maximize the degree of hardware reusability by fusing multiple two-input multipliers and a multi-input adder into one two-input multiplier and one two-input adder. With RNA, we demonstrated a hardware implementation of a three-layer 51-30-12 artificial neural network using only thirty physical RNA neurons. A quantitative design space exploration in area, power dissipation, and speed between the proposed RNA and three other implementations representative of different reusable hardware strategies is presented and discussed. An RNA ASIC was implemented using 45nm CMOS technology and verified on a Xilinx Virtex-5 FPGA board. Compared with an equivalent software implementation in C executed on a mainstream embedded microprocessor, the RNA ASIC improves both the training speed and the energy efficiency by three orders of magnitude, respectively. The real-time and functional correctness of RNA was verified using real ECG signals from the MIT-BIH arrhythmia database.

Brain-computer interfaces (BCIs) are able to translate cerebral cortex neural activity into control signals for computer cursors or prosthetic limbs. Such neural prosthetics offer tremendous potential for improving the quality of life for disabled individuals. Despite the success of laboratory-based neural prosthetic systems, there is a long way to go before it makes a clinically viable device. The major obstacles include lack of portability due to large physical footprint and performance-power inefficiency of current BCI platforms. Thus, there are growing interests in integrating more BCIs components into a tiny implantable unit, which can minimize the surgical risk and maximize the usability. To date, real-time neural prosthetic systems in laboratory require a wired connection penetrating the skull to a bulky external power/processing unit. For the wireless implantable BCI devices, only the data acquisition and spike detection stages are fully integrated. The rest digital post-processing can only be performed on one chosen channel via custom ASICs, whose lack of flexibility and long development cycle are likely to slow down the ongoing clinical research. This thesis proposes and tests the feasibility of performing on-chip, real-time spike sorting/neural decoding on a programmable wireless sensor network (WSN) node, which is chosen as a compact, low-power platform representative of a future implantable chip. The final accuracy is comparable to state-of-the-art open-loop neural decoder. A detailed power/performance trade-off analysis is presented. Our experimental results show that: 1)direct on-chip neural decoding without spike sorting can achieve 30Hz updating rate, with power density lower than 62mW/cm2; 2)the execution time and power density meet the requirements to perform real-time spike sorting and wireless transmission on a single neural channel. For the option of having spike sorting in order to keep all neural information, we propose a new neural processing workflow that incorporates a light-weight neuron selection method to the training process to reduce the number of channels required for processing. Experimental results show that the proposed method not only narrows the gap between the system requirement and current hardware technology, but also increase the accuracy of the neural decoder by 3%-22%, due to elimination of noisy channels.

We have fabricated electrical devices based on thermal chemical vapor deposition (TCVD) grown single walled carbon nanotubes (SWCNTs). Long SWCNT are utilized to analyze electrical transport properties and extract contact data including Schottky Barrier heights (SBHs) and contact resistance. For all studies performed, multiple contact metals were used, and tens to hundreds of devices were fabricated on single CNT. This mass production method allows comparison of results, as well as greater options in device analysis. To analyze SBHs at carbon nanotube metal contacts, field effect transistor (FET) devices were examined using AFM, low temperature measurements in closed cycle refrigerator (CCR), and electrical characterization. SBH is measured on carbon nanotubes with multiple metal contacts for comparison purposes, with barriers extracted via low temperature activation energy measurements and nonlinear curve fitting using the program Origin. Two methods were utilized in the fabrication of carbon nanotube devices for the SB study. The first incorporated both electron beam lithography (EBL) for exposures and focused ion beam (FIB) for deposition of lead lines between CNT contacts and large probe pads. The second method used only EBL to prevent the ionic exposure common in FIB. The effect of using EBL with devices incorporating CNT has also been investigated. The effect on metallic and semiconducting CNT exposure in the channel of the transistor devices was examined and a physical mechanism for the variations discussed. We show that the subsequent generation of trap states along the CNT channel varies the conduction mechanism of the nanotube and has a significant effect on device performance. Metallic and Semiconducting CNT react very differently, with an apparent increased localization in the metallic tubes responsible for dramatic decreases in conductance.

The purpose of this study is to investigate the human manual control strategy when balancing an inverted pendulum under time critical constraints. The strategy was assessed through the quantification and evaluation of human response while performing tasks that require fast reaction from the human operator. The results show that as the task becomes more difficult due to increased time delay or shortened pendulum length, the human operator adopts a more discrete-type strategy. Additionally, dissimilarities between control of a short pendulum and a delayed pendulum are identified and discussed. Finally, the discrete-control mechanism is interpreted by relating the observed human responses to human-performance models. These results can be applied to systems requiring human interaction, such as teleoperation, which could be designed to maximize human response.

Functional verification is generally regarded as the most critical phase in the successful development of digital integrated circuits. The increasing complexity and size of chip designs make it more challenging to find bugs and meet test coverage goals in time for market demands. These challenges have led to more automated methods of simulation with constrained random test generation and coverage analysis. Recent goals in industry have focused on improving the process further by applying Coverage Directed Test Generation (CDG) to automate the feedback from coverage analysis to test input generation. Previous research has presented Bayesian networks as a way to achieve CDG. Bayesian networks provide a means of capturing behaviors of a design under verification and making predictions to help guide test input generation to reach coverage goals more quickly. Previous research has shown methods for defining a Bayesian network for a design domain and generating input parameters for dynamic simulation. This thesis demonstrates that existing commercial verification tools can be combined with a Bayesian inference engine as a feasible solution for creating a fully automated CDG environment. This solution is demonstrated using methods from previous research for applying Bayesian networks to verification. The CDG framework was implemented by combining the Questa verification platform with the Bayesian inference engine SMILE (Structural Modeling, Inference, and Learning Engine) in a single simulation environment. SystemVerilog testbenches and custom software were created to automatically find coverage holes, predict test input parameters, and dynamically change these parameters to complete verification with a fewer number of test cases. The CDG framework was demonstrated by performing verification on both a combinational logic design and a sequential logic design. The results show that Bayesian networks can be successfully used to improve the efficiency and quality of the verification process.