This thesis presents results on the effects of low-temperature gettering processes on minority carrier lifetime in multicrystalline silicon. Wafers are sourced from different height positions of a commercially-grown ingot. The distribution of different key material properties including bulk lifetime, interstitial iron concentration, and dislocation density are characterised and are found to vary widely with ingot height position. Lifetimes are measured by using temporary liquid iodine-ethanol passivation at room temperature or silicon nitride films deposited by plasma-enhanced chemical vapour deposition. Lifetimes are lower in samples from the extrema of ingot than the centre parts. Interstitial iron concentrations are found to be highest in the bottom samples and lowest at the centre of the ingot. Dislocation density is lowest at the bottom of the ingot and increases with ingot height position. In as-grown wafers, low-temperature gettering can improve lifetime substantially in relatively poor samples from the extrema of the ingot. Iodine-ethanol passivation is used to separate thermal effects of annealing from any bulk passivation which may occur during surface passivation from lifetime measurement. The largest relative lifetime improvement (from 5.5 μs to 38.7 μs) is achieved in material from the bottom of the ingot with annealing at 400°C for 35 h. The benefit of low-temperature annealing is marginal for middle samples. Bulk interstitial iron concentrations decrease by up to 2.1 order of magnitude in the bottom samples. The reduction in interstitial iron concentration is not found to be systematically dependent on annealing temperature. For bottom samples a good correlation between the changes in lifetime and interstitial iron concentration is found. The effects of different passivation schemes on low-temperature gettering is also investigated. The results show that starting lifetime and interstitial iron concentration strongly depends on the choice of passivation scheme. The effect of different surface passivation schemes is more pronounced in relatively high lifetime samples. In samples from the bottom of the middle of the wafer, lifetime improves from 113 μs to 171 μs with silicon nitride passivation upon annealing at 400 °C for 25 h. Supporting results from secondary ion mass spectrometry show that substantial concentrations of iron exist in the silicon nitride film after low-temperature annealing. This suggests silicon nitride layer might be an additional gettering centre for interstitial iron. This thesis also studies the effects of low-temperature annealing combined with a standard phosphorus diffusion process to form an emitter. Lifetime in samples from the top and bottom of the ingot can be improved by annealing at 300°C and 400°C even after the phosphorus diffusion process. The largest improvement is from 54 μs to 78 μs upon post-diffusion annealing of bottom samples at 300°C, and the results suggest gettering of impurities other than interstitial iron is likely. The phosphorus diffused emitter layers do not act as effective additional gettering sites for interstitial iron upon low-temperature annealing. The lifetime improvement upon pre-diffusion annealing is retained after the diffusion process. In summary, low-temperature annealing has the potential to improve the lifetime in as-grown multicrystalline silicon and after a phosphorus diffusion gettering under some conditions. Low-temperature annealing thus provides a potential low cost route to improve multicrystalline solar cell efficiencies.

Condition monitoring in power electronics is increasingly becoming a critical component of reliable power electronics both in traditional discrete and DBC packages as well as in pressure-packages. Condition monitoring involves on and off-line assessment of the state of health of the power module in an effort benchmark the reliability performance of the module (if off-line) or to prolong its useful operating life (if on-line). One widely acknowledged method of condition monitoring involves the use of temperature sensitive electrical parameters (TSEPs) to estimate the junction temperature and hence, the junction to case thermal impedance as well as on-state electrical resistance. However, for TSEP based condition monitoring to become reality, a significant amount of electrothermal characterisation of modern power devices is necessary and that is where this thesis makes a valuable contribution, especially for new SiC power devices with relatively unknown thermal characteristics in alternative packages like press-packs. TSEPs including diode/transistor on-state voltage drop, turn-on current switching rate, gate current/voltage switching transients etc., depend on the physics of the power devices and can vary from device to device depending on whether they are bipolar, unipolar, silicon or SiC. The on-state voltage drop of some devices exhibits a negative temperature coefficient, while others exhibit a positive one depending on the value of the Zero Temperature Coefficient (ZTC) point exhibited in the forward characteristics. The Zero temperature coefficient results from the interaction between junction voltages which reduce with temperature (due to increased intrinsic carrier concentration from bandgap narrowing) and parasitic series resistances which increase with temperature (due to mobility and ambipolar diffusion length reduction with temperature). This thesis shows that SiC power MOSFETs have the unique property of switching on faster at higher temperatures whereas the converse is true for silicon MOSFETs and IGBTs. Hence, the turn-on current switching rate has been proposed as a TSEP in SiC MOSFETs. The impact of parasitic inductance on the temperature sensitivity of the turn-on switching rate is also investigated and recommendations are made for the use of intelligent gate drivers with alterable gate driver impedances for implementing condition monitoring. This thesis also investigates the impact of junction temperature variation in parallel connected power devices on the accuracy of the TSEP for the entire module and how the gate driver could be used to improve the temperature sensitivity of determined electrical parameters. In the context of pressure-packaged assemblies, where the thermal impedance is inextricably linked with the electrical impedance, this thesis presents the electrothermal characterisation of SiC Schottky diodes. Both a single chip and a multichip press-pack prototypes have been designed and tested, including the evaluation of different intermediate contact materials, namely Aluminium Graphite and molybdenum. The impact of pressure imbalance and device temperature characteristics (ZTC point) on electrothermal stability of parallel devices are explored in this thesis.

Due to concerns of climate change, an increasing number of distributed generation (DG) units have been installed globally in the last two decades. This lead to issues on many aspects in the distribution network operation and management, in which the two most concerned issues are the voltage violation and fault level increase. To regulate the voltage profile and control power flow in the network, power electronic devices based soft open point (SOP) has been developed and trailed in the distribution network according to recent research. These studies mainly focused on the functions and control strategies of the power electronic compensator. However, the protection strategy and power loss of the power electronic device used in the SOP have been rarely investigated. In addition, conventional fault analysis neglects the fault current contributed from domestic load, which is hindering, and the increase DG penetration. In this work, the short-circuit behaviour of small sized induction machines in domestic load has been studied. A method for the estimation of fault current by load with higher accuracy is developed. Furthermore, the short-circuit behaviour of small and medium sized synchronous machine based DG has been investigated. A recommendation on the first symmetrical short-circuit current for synchronous machine based DG has been proposed for the situation when detailed information of the DG is unavailable. A study on the fault level change due to changes in both generation and load in the UK distribution network has been conducted and the results are presented. Regarding the SOP protection strategy, two topologies using thyristor crowbars in the protection of static synchronous series compensator (SSSC) based SOP are proposed. For these two protection topologies, the feasibility of the strategy has been thoroughly analysed in several aspects. The results indicate that with proper selection in the thyristor crowbar and coupling transformer, these protection topologies are feasible and effective. To investigate the power loss for the power electronic devices, several cases have been studied based on 11kV distribution network model with back to back voltage source converter (B2B VSC) based SOP. The results show that in most cases, the utilisation of B2B VSC based SOP can reduce the total network loss. Nevertheless, when the DG penetration level or the imbalanced loading level between two feeders is low, the B2B VSC will further increase the total network loss. Finally, one of the solutions to the fault level issue due to the DG installation is to employ fault current limiter (FCL) into the distribution network. The power loss of saturated iron core FCL has been analysed. The results show that the power loss of a saturated iron core FCL can be 1% or even less of the transferred power. It is more efficient compared to the power semiconductor type for the fault current mitigation.

A surface x-ray diffraction (SXRD) study has been conducted investigating the structural properties of Sb thin-film deposition onto InAs(111)B-(1 1) surfaces via molecular beam epitaxy (MBE). It was found that epitaxy was not possible for deposition at high substrate temperatures ( 220 C), which instead resulted in substitution of the surface As atomic sites. Successful epitaxy required a combination of deposition at room temperature, followed by a short anneal using a substrate temperature of 200 C . An increase in film thickness was found to decrease the difference between the intra-bilayer and inter-bilayer distances within the Sb _lm. MBE growth of MnSb onto In0:5 Ga0:5 As(111)A-(2 2) surfaces has been investigated, with a focus on the effect of substrate temperature (Tsub ) and flux ratio JSb=Mn on thin _lm growth. It was found that slightly different settings are required compared to growth on GaAs(111) substrates, with intermixing between the overlayer and substrate being observed on multiple samples. A SXRD study comparing the growth of MnSb on GaAs(111)A and GaAs (111)B surfaces was conducted . Reflection high energy electron diffraction (RHEED) observations during deposition indicate early-stage layer-by-layer growth is only attainable on GaAs(111)A substrates. SXRD measurements confirmed that this difference in early-stage growth process affects the quality of the overall layer, even for thicker films. A SXRD study of multi-layer heterostructure growth was conducted, focussing on the deposition of GaAs onto MnSb/Ga(In)As(111)A and MnSb/GaAs(001) virtual substrates. Despite poor surface, morphology, deposition of crytalline material was achieved. It was found that for (111)A virtual substrates a shift in the central n-MnSb layer was observed, which is attributed to the formation of MnAs at the MnSb surface. For the (001) virtual substrate 3D island growth was observed, and a plausible epitaxial relation between the MnSb(1101) and GaAs(001) surfaces is presented.

It is necessary for power laterally diffused MOSFETs (LDMOSFETs) to operate efficiently and reliably in high temperature (< 300 °C), hostile environments such as those found in downhole, space, automotive and aerospace applications. Currently, silicon-oninsulator (SOI) technology is a dominant method to achieve this goal due to low leakage current and complete electrical isolation. However, the buried oxide (BOX) layer causes self-heating, which can impact device performance, cause thermal runaway and shorten device lifetime. To address this issue, one solution is to combine a silicon thin film with a semi-insulating (SI) SiC substrate, forming the Si/SiC architecture. LDMOSFETs built on this substrate are expected to deliver much better thermal performance, with electrical isolation comparable to the SOI case. However, the Si/SiC LDMOSFETs do not have a strong substrate assisted depletion effect, which can result in poorer electrical performance than those of the Reduced Surface Field (RESURF) bulk-Si and SOI LDMOSFETs. This thesis investigates the PN and SOI RESURF layouts and uses them to optimise 190 V and 600 V Si/SiC LDMOSFETs. DC and transient modelling will be conducted on the optimised Si/SiC and their SOI and bulk-Si equivalents. Based upon this, several comparative studies are conducted on their simulation results to see the effects of the Si/SiC architecture on the LDMOS designs. The comparative studies are made on the 600 V Si/SiC LDMOSFETs and their bulk Si and SOI equivalents. It is shown that the Si/SiC devices have the potential to operate with an off-state leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariable with substrate potential up to −200 V, which behaves similar to the bulk-Si LDMOS at 300 K. A clamped-inductive switching circuit is simulated for the Philips SOI and the Si/SiC equivalent. It is shown that even though the SOI has a smaller chip area and suffered from strong substrate effects during the transient state, the two devices had similar currents and power dissipations at the gate, drain and source. The turn-on losses are higher than that of the turn-off losses due to the presence of parasitic capacitors. However, these similarities do not lead to similar thermal responses in both devices and the SOI is heated up at a much faster rate. By contrast, the SiC substrate in the Si/SiC behaves like an embedded heat sink regulating device temperature close to that of the ambient environment (423 K). In the high current condition, the peak temperature in the Si/SiC is 425 K, lower than 463 K in the SOI, thereby increasing reliability. The comparative studies are carried out on the 190 V LDMOSFETs in SOI, Si/SiC, Partial SOI (PSOI) and PSOSIC technology, based upon a capacitive and an inductive switching circuit. It is revealed that in spite of having a chip area 75% larger than the SOI structure, the Si/SiC solution undergoes negligible heating in any of the switching conditions simulated, exhibiting a very high energy capability. By contrast, the 22% area increase in the PSOSiC does not considerably change the way the energy is handled. This indicates that the Si/SiC is much more effective than PSOI and PSOSIC in dealing with the transient heating.

The use of power electronics is increasing in an exponential form. The need of power devices to be faster, block higher voltages and reduce their losses is leading to a fundamental change in the device architecture and choice of material. Gallium nitride and Silicon carbide are the materials of choice and commercial devices are available. Diamond and gallium oxide are materials that are considered for the future and they will push the boundaries of power electronics even further. There are well developed tools that can simulate the behavior of a power device is a very accurate way and they can calculate losses, turn on and turn off times and the over behavior of the device during switching. These tools are usually very complex and difficult to learn. They also cannot provide very quick results and they heavily depend on the amount of computational power that is available to the user. Due to their complexity they can only calculate a few maybe a couple of switching events before they run out of computational memory. This thesis is trying to solve this problem by using simple state space analysis and using a lot simpler equations and computational methods to predict the behaviour of the device. The simplicity of these calculations can give faster results that is very helpful in a lot of cases. Also tools that calculate the temperature of the power devices have been created again using simpler mathematical equations that can evaluate the device temperature. So a fast, reliable and simple way of estimating the device behavior has been created. Another aspect that has been covered in this thesis is the reliability of power devices under unconventional conduction. A number of devices have been tested under avalanche mode conduction and an extensive comparison has been made between device architecture, MOSFET vs IGBT, Si vs SiC, Repetitive vs single avalanche events. Also these tests have been conducted in different ambient temperatures so the effect of temperature has been investigated thoroughly as well.

This thesis is focused on signal-to-noise (S/N) enhancement of III - V semiconductor photodetectors for use in gas sensing applications within a specific frequency band of interest in the mid infrared (MIR) range. The semiconductor photodetectors can be grown as homostructures, but experiments have shown a clear benefit to using heterostructures and the quantum barriers they incorporate to reduce diode leakage. The proposed method of enhancement is the use of waveguide coupling with different resonating materials of different shapes, known as micro-antennas. The antennas were designed to be responsive to an incoherent light source, such as LEDs. State of the art examples were considered to optimise all aspects of the antenna design (i.e. the length, thickness, pitch and the dielectric constant) to reduce surface scattering and enhance coupling. The experimental demonstration requires consideration of maximisation of energy coupling into the intrinsic regions of Al0.05In0.95Sb (Aluminium Indium Antimonide) semiconductor diodes. The theoretical results were generated as a hybrid model to ensure full calibration and accuracy. Measurements of the semiconductor attenuation coefficient were taken externally and applied to sophisticated Electromagnetic (EM) simulation software. The EM simulations were done using Computer Simulation Technology (CSTTM). It was used to verify the expected results for different antenna sizes and to provide confidence for the outcomes of more elaborate design enhancements, including large scale selective removal of the semiconductor. Selective removal capitalises on energy coupling towards a specific position and depth close to the surface. Further work into investigating far field manipulation effects of antenna design applied to isotropically stimulated LEDs was included. Theoretical and experimental studies are reported that show that the antennas needed to be of an appropriate size to resonate at the appropriate wavelength. The variation with the antenna’s dielectric properties as well as the polarisation angle and trajectory angle of the stimulating source are reported. There are numerous shapes to be considered for various intended applications. The antenna design that has suited our specific purpose has an efficient packaging density, is responsive to a non-collimated stimulation source, is made out of low cost conductive materials, is fabricated in a commercially viable way and provides consistent and stable results.

Sutton introduced EL CID in the 1970's. This thesis records the development of EL CID theory, with particular reference to its application to large, salient-pole, water-turbine driven, electrical machines, known as hydrogenerators. Factors are identified and clarified which otherwise may cause misunderstanding of hydrogenerator stator core interlamination insulation condition. Features discussed, with reference to their impact upon the detected EL CID signal, are alternative forms of excitation winding of the stator core, its constructional features, including core build bars (or key bars), core segmentation, proximity of ferrous components, plus ancillary matters such as the location of brake/jack units, the degree of machine assembly, whether in or out of the operational situation, the extent of the machine enclosure, and the presence of the stator winding and rotor-mounted salient poles. Although satisfactory application of EL CID to turbogenerators was achieved in the 1970's, anomalies arose when applied to salient-pole machines, due to shorter stator winding end-overhang, its multi-parallel circuits, and also the disincentive of realignment of the rotor if removed, making access to the stator bore and accurate location of the excitation cable more difficult. When present, joints in very large hydrogenerator stator frames and cores, for transportation, made analysis of EL CID results particularly difficult. The problem presented by core joints arose in the initial factory demonstration of application of EL CID to hydrogenerators. The solution recognises the interdependence of the two orthogonal EL CID signal components, which indicate EL CID as analogous to a transformer, with two short-circuited secondary windings; one for interlamination fault current (designated "delta"), the other being the stator winding, when present. In order to draw the phasor diagram with reference to the secondary side of the analogous transformer, the direction of the excitation phasor is reversed, since the fault current is detected in a secondary circuit. Application of standard transformer theory produces an appropriate EL CID phasor diagram, in various forms, depending upon the particular test circumstance. In this context, the significant concept of a line for which interlamination fault current (delta) is zero (i.e. a zero delta line) was introduced. The two orthogonal EL CID signals, designated PHASE and QUAD, are plotted on equal scales; unless related appropriately by a technique described, which takes the difference into account, to ensure the highest accuracy. Evaluation of delta indicates the effectiveness of core repairs, which supports the usefulness of the EL CID technique when applied to hydrogenerators, as well as turbogenerators. At core joints, the detected maximum fault current (deltamax) is usually appreciably greater than the traditional acceptance criterion of 100 mA. This is discussed, and the conclusion drawn that the distribution of delta along the core length provides an adequate indication of any weak region of interlamination insulation. The practise of routinely resetting the Phase Reference for an EL CID test is examined, and found to be not acceptable, unless the results are subsequently referred back to the basic reference. As a final demonstration of the EL CID technique usefulness, the analysis of results from a core joint, where there was an imposed artificial fault, identifies the location concerned.

Lithium-ion battery packs are increasingly being used for high power and energy applications such as electric vehicles and grid storage. These battery packs consist of many individual cells connected in series and/or parallel. Manufacturing tolerances and varied operating conditions mean that each cell will be different one from another, being able to store different amounts of energy and deliver different amounts of power. This also means some cells will finish charging or discharging before others, resulting in unutilised energy in the remaining cells. Passive balancing systems are often used in multi-cell battery packs to ensure that all of the cells can be fully charged. However, this does not account for differences in cell capacity, meaning that not all cells will be fully discharged. Active balancing systems have been developed to transfer energy between the cells, in theory allowing for stronger cells to compensate for weaker ones. However, their perceived cost and complexity have prevented them from being widely adopted in commercial applications. In this work, an innovative control strategy was developed to determine how and when to energy balance a set of battery cells, with the aim of maximising battery pack energy utilisation. A model-based control system was designed, using state of charge to evaluate the level of energy imbalance between cells. Real-time implementation using second-hand electric vehicle cells and commercial balancing hardware demonstrated that the control strategy can decrease the amount of unused charge in the battery pack from 8% with passive balancing to 1% with active balancing, which has significant impact for battery pack energy throughput, physical size, mass, and long-term health.

A proton exchange membrane (PEM) fuel cell is an electrolytic cell that converts chemical energy of hydrogen reacting with oxygen into electrical energy, without producing any greenhouse gases. To meet increasingly stringent application needs, improved performance and increased efficiency are paramount. Computational fluid dynamics (CFD) is an ideal means for achieving these improvements. In this thesis, a comprehensive CFD-based numerical toolbox that can accurately simulate the major transport phenomena which take place within a PEM fuel cell is presented. The tool is developed using the Open Source Field Operation and Manipulation (OpenFOAM) software (a free open-source CFD code) which makes it very flexible and well-suited for use by fuel cell manufacturers and researchers to rapidly gain important insights into the cell working processes which are crucial to the cell optimization. The toolbox includes a three-dimensional (3D) non-isothermal model for both single-phase flow and multiphase flow simulations. Case studies in steady-state operating conditions were conducted with both models. The results for the distribution of velocity, pressure, chemical species mass fractions, Nernst potential, local current density and temperature, cathode exchange current density, activation overpotential, membrane ionic conductivity, ohmic overpotential, cathode limiting current density, and concentration overpotential are as expected, for both flow models. The results of mesh independence studies indicate that in terms of the cell performance, the case study mesh provides adequate resolution. Qualitative comparisons were made between numerical and experimental results taken from the literature, and the results obtained with the multiphase flow model. Good agreement was obtained over the entire range of the cell operation. Furthermore, a parametric study with the multiphase flow model revealed the effects of operating temperature and pressure, charge transfer coefficient, gas diffusion layer thickness and porosity, catalyst layer porosity, stoichiometric flow ratio, flow configuration, and concentration constant on cell performance. Interestingly, it was found that: the counter-flow flow configuration results in reduced cell potential at high current densities compared to the co-flow flow configuration; and the value of the concentration constant (c) greatly affects the proportions between the activation, ohmic and concentration losses. A c value between 0.2 and 0.3 can ensure realistic proportions between the three overpotentials in the fuel cell which are crucial in shaping the cell polarization curve. The PEM fuel cell numerical toolbox presented in this thesis has many novel features that enhance the physical realism of the simulations. The models that are provided within the toolbox can serve as a basis to develop other features such as improved catalyst and membrane models. More importantly, since the toolbox has been developed using OpenFOAM, it can form a framework for research and development which is not possible with commercial software. The work therefore contributes to achieving the objectives outlined in the International Energy Agency (IEA, France) Advanced Fuel Cell Annex 37 which promotes open-source code modelling of fuel cells. The source code for the single-phase flow model and the multiphase flow model are available at http://dx.doi.org/10.17632/3gz7pxznzn.1 and http://dx.doi.org/10.17632/c743sh73j8.1, respectively.