<p>In modern wireless communication technology, designing low power, high frequency transceivers while exhibiting low noise is still one of the challenging topics in RF systems. Compared to other technologies, CMOS VCO has a poorer performance at phase noise measurements. Therefore, improving phase noise becomes a very important issue in designing a high quality YCO.</p> <p>This work describes and compares the available models to realize low phase noise oscillators. On this basis, the possible criteria for reducing phase noise are discussed.</p> <p>In this thesis, we explore phase noise fluctuations at the offset range of 10kHz to lOOK Hz for six 2.4 GHz LC-tuned YCOs, fabricated in O.18μm standard mixed-signal CMOS process. We compare the phase noise performance of all six circuits and draw conclusions about reducing phase noise.</p> <p>The measurement results show that the Q factor of the inductor has the most significant effect on reducing phase noise fluctuations. The next important parameter is the capacitor. The resistors in the VCO do not affect phase noise fluctuations.</p> / Master of Science (MS)

<p>In this thesis, we present the applications of low density graph codes in two different types of source coding problems. First, we consider asynchronous Slepian-Wolf coding where the two encoders may not have completely accurate timing information to synchronize their individual block code boundaries, and propose LDPC design in this scenario. A new information-theoretic coding scheme based on source splitting is provided, which can achieve the entire asynchronous Slepian-Wolf rate region. Unlike existing methods based on source splitting, the proposed scheme does not require common randomness at the encoder and the decoder, or the construction of superletter from several individual symbols. We then design LDPC codes based on this new scheme, by applying the recently discovered source-channel code correspondence. Second, we consider the lossy source coding problem. In contrast with most prior work that has focused exclusively on the binary uniformly distributed source, we address the problem of lossy coding for sources with arbitrary alphabets and distributions. Built upon the idea of approximating the optimal output distribution indicated by the rate-distortion theory with a uniform distribution over a larger alphabet, we propose a multilevel coding scheme using LDGM codes that can approach the rate-distortion limit for a general source. Experimental results validate the effectiveness of both proposed methods.</p> / Master of Applied Science (MASc)

<p>Target tracking in high clutter or low signal-to-noise environments presents many challenges to tracking systems. Joint Maximum Likelihood estimator combined with Probabilistic Data Association (JML-PDA) is a well-known parameter estimation solution for the initialization of tracks of very low observable and low signal-to-noise-ratio targets in higher clutter environments. On the other hand, the Joint Probabilistic Data Association (JPDA) algorithm, which is commonly used for track maintenance, lacks automatic track initialization capability. This paper presents an algorithm to automatically initialize and maintain tracks using an integrated JPDA and JML-PDA approach that seamlessly shares information on existing tracks between the JML-PDA (used for initialization) and JPDA (used for maintenance) components. The motivation is to share information between the maintenance and initialization stages of the tracker, that are always on-going, so as Lo enable the tracking of an unknown number of targets using the JPDA approach in heavy clutter. The effectiveness of the new algorithm is demonstrated on a heavy clutter scenario and its performance is tested on negibouring targets with association ambiguity using angle-only measurements.</p> / Master of Applied Science (MASc)

<p>The Multi Frame Assignment (MFA) tracker solves the data association problem as a constrained optimization for fusing multiple sets of data to the tracks with an Interacting Multiple Model (IMM) estimator.</p> <p>With the rapid development of parallel computing hardware such as GPU (Graphics Processor Unit) in recent years, GPGPU (General-Purpose computation on GPU) has become an important topic in scientific research applications. However, GPU might well be seen more as a cooperator than a rival to CPU. Therefore, exploiting the power of CPU and GPU in solving the MFA tracker algorithm based on CPU-GPG integrated computing environment is the focus of this thesis.</p> <p>In this thesis, a parallel MFA algorithm implementation based on CPU-GPU integrated computing model to optimize performance is presented. The results show that the algorithm increases the average performance by 10 times compared with the traditional algorithm. Based on the results and current trends in parallel computing architecture. it is believed that efficient use of CPU-GPU integrated environment will become increasingly important to high-performance tracking applications.</p> / Master of Applied Science (MASc)

<p>Digital logic techniques emphasizing economical implementation as applied to Walsh function generation and a digital Walsh analyzer are considered. The Walsh function generator design presented features sequency programmability of the dual orthogonal output and the generator operated in the megahertz range with an orthogonality error measurable in nanoseconds. The generator is a central component of the digital Walsh analyzer which provides a pair of Walsh coefficients after only two cycles of an unknown periodic waveform. All analyzer functions, including timing, sample processing and Walsh function generation are provided complete in only seventy integrated circuit modules.</p> / Master of Engineering (ME)

<p>This thesis investigates the electrochemical performance of flexible implanted electrodes for the purpose of neuromuscular electrical stimulation. Electrodes performance is validated through their conductivity, stability, and charge delivery capacity (CDC) to avoid irreversible faradaic reactions during stimulation. To study these requirements, electrodes were fabricated by depositing platinum (Pt), gold (Au) and titanium (Ti) thin films on the flexible liquid crystal polymer (LCP) substrate. Their electrochemical properties were then studied using surface and interface characterization techniques including atomic force microscopy (AFM), electrochemical impedance spectroscopy (EIS), cyclic voltammetry (CV) and a theoretical model. The EIS results demonstrate that larger electrodes provide higher conductivity and double layer capacitance. In terms of material, Pt offers the best conductivity in neuromuscular stimulation frequencies of 1- 250 Hz, followed by Ti and Au, respectively. Above 250 Hz, similar values of conductivity is offered by the electrodes. This material dependence of impedance magnitude is related to the surface morphology, structural quality and deposition parameters of the electrodes and is explained using surface roughness measurements and interface model parameters. Electrode long-term stability is explored by regular EIS measurements through 42-day experiments. With progressing time, an increase in surface roughness, decrease in chargetransfer resistance (Rct) and capacitive quality (¯) are observed due to the change in capacitive and faradaic behaviors. However, in the comparative evaluations, Au electrode shows the most consistency in keeping its capacitive behavior to perform reversible charge transfer, followed by Pt and Ti, respectively. Further, cyclic voltammetry (CV) curves were used to understand the charge transfer reactions and calculate charge delivery capacities (CDC) of Pt, Ti and Au. Pt with highest CDC value suggests the best electrochemical reversibility followed by Au and Ti. In the case of deposition pressure, for Ti electrode, lower deposition pressure yields higher charge delivery capacity. These results may make lower pressure deposited Pt electrode with high conductivity and CDC the best material for the short term applications of neuromuscular electrical stimulation, while Au possessing improved stability but lower conductivity and CDC is suggested for long term applications. This result provides deeper insight into the design and miniaturization of electrochemical electrodes for the further development of neuromuscular prostheses.</p> / Master of Applied Science (MASc)

<p>The purpose of this thesis is to develop a practical receiver for Rayleigh fadin?; channels. which does not exhibit the error floor found for conventional receivers in this channel. A model of a general time and frequency-selective channel is developed, and the opt.imal receiver structure for a time-selective channel is derived for general signalling. The theoretical performance of a standard and maximum likelihood receiver is analyzed for the case of f\Iary differential phase shift keying. A recursive, channel adaptive version of the optimal receiver is derived, and through simulation, its performance is compared to theoretical expectations . Results indicate that such a receiver will reduce the receiver error floor severnl orders of magnitude at typical channel signal-to-noise ratios.</p> / Master of Engineering (MEngr)

<p>The neurophysiological basis of sensorineural hearing loss is thought to be hair cell damage or stria vascularis atrophy in the cochlea. The normal cochlea is responsible for a very complex, dynamic, nonlinear analysis and coding of acoustic signals, which is distorted by cochlear impairment. To overcome hearing loss, a typical hearing aid provides linear gain or some simple form of dynamic compression. However, such simple processing cannot fully compensate for the effects of cochlear impairment. In this thesis, machine learning is used to investigate more optimal speech processing schemes for hearing aids.</p> <p>A model of the auditory periphery is utilized to develop a set of neural predictors of human speech intelligibility. These are shown to have similar accuracy to acoustic predictors of intelligibility such as the articulation index. The neural predictors are then used as error metrics in a machine learning framework to train simple linear and compressive hearing aid algorithms. The results are consistent with empirically derived prescriptions for hearing linear gain and compression.</p> <p>It thus appears that to develop speech processing algorithms that provide greater benefits than those currently available in hearing aids, it is necessary understand more fully the distortions that are occurring in the cochlea due to hearing loss and to develop processing algorithms that specifically target compensation of these distortions. An analysis of the differences in compression, suppression and adaptation in the normal and impaired cochlea is performed using the model of the auditory periphery, and specific distortions are quantified. From this analysis, several speech processing algorithms are proposed that may more fully compensate for the effects of cochlear impairment on the neural representation of speech.</p> / PhD Otolaryngology (PhDOtol)

<p>There is a tremendous demand for Internet core nodes to provide quality-of-service (QoS) guarantees for multimedia services, and to provide high switching capacity that makes use of the virtually unlimited bandwidth of optical fibers. The Internet's Success depends on the deployment of high-speed switches and routers that meet these two demands. We address theoretical and practical aspects of packet switch scheduling in high-speed data networks.</p> <p>First, we address short-term fairness III QoS scheduling for input-queued (IQ) switches. We show that existing practical scheduling algorithms for Internet routers with IQ switches are unfair over short time scales and potentially lead to increased jitter. Subsequently, we present a scheduling policy based on credit-based fair queueing that provides better short-term fairness in QoS scheduling than existing solutions with comparable complexity. A flow-based iterative credit-based fair scheduler (iCBFS) is proposed for crossbar switches, that provides fair bandwidth distribution among flows at a fine granularity and achieves asymptotically 100% throughput, under uniform traffic. To reduce the implementation complexity of iCBFS, we present a port-based version of iCBFS that is tailored towards high-speed hardware implementation.</p> <p>Second, we address the problem of fair scheduling of packets in Internet routers with IQ switches and unity speedup. Scheduling in IQ switches is formulated as tracking the behaviour of an output-queued (OQ) switch that provides optimal performance. We present the notion of "lag" as a performance metric that measures the difference between a packet's departure time in an IQ switch over that provided by an OQ switch. We prove that per packet mean lag is bounded for a maximum weight matching scheduling policy that uses lag values for its weights and derive a bound on the mean lag value using a Lyapunov function technique. Furthermore, we propose a simple heuristic tracking scheduling policy and evaluate its performance by simulation.</p> <p>Finally, we present a novel distributed scheduling paradigm for Internet routers with IQ switches, called Cooperative Token-Ring (CTR) that provides significant performance improvement over existing scheduling schemes with comparable complexity. In classical token-ring based scheduling for IQ switches, a separate token ring (an arbiter) is used to resolve contention for each shared resource (i.e., an output port). Although classical token-ring based scheduling achieves fairness and high throughput for uniform traffic, under non-uniform traffic the performance degrades significantly. We show that by using a simple cooperative mechanism between the otherwise non-cooperative token rings (arbiters) the performance can be significantly improved and the scheduler is able to dynamically adapt to any non-uniform traffic pattern. To provide adequate support for rate guarantees in IQ switches, we present a Weighted Cooperative Token-Ring (WCTR), a simple hierarchical scheduling mechanism. Finally, we analyze the hardware complexity introduced by the proposed CTR scheduling and describe an optimal hardware implementation for an N x N switch implementing a CTR scheduler. We show that the hardware time complexity introduced by the proposed Cooperative mechanism is 8 (log N). iv</p> / Doctor of Philosophy (PhD)

<p>This thesis develops a systematic and self-consistent framework for the RF noise characterization, modeling and simulation of deep sub-micron MOSFETs. The techniques and procedures developed in this thesis are general and can be applied to the high-frequency noise characterization of any active device. In general, there are five topics presented in this research work. First, a systematic calculation method that can directly calculate the noise parameters - minimum noise figure NFmin, equivalent noise resistance Rn, optimized source resistance Ropt and reactance Xopt - of an active device using matrix computation is presented. This method is general and can calculate the noise parameters of any noisy two-port network including correlated noise sources.</p> <p>Second, a new de-embedding procedure based on a cascade configuration to remove the parasitic effects of the probe pads and the metal connections from the measured noise and s-parameters is developed. Two "THRU" dummy structures are proposed in the new de-embedding procedure and no equivalent circuit models for the probe pads and the interconnections are required. From theory, it has no frequency limitation (or it is valid to the frequency at which the discontinuity effect has to be taken into account) and works for any geometry of interconnection designed without introducing more dummy structures.</p> <p>Third, two extraction methods to obtain the spectral densities of the channel noise, induced gate noise and their noise correlation from the intrinsic noise parameters as a function of frequency and bias condition are presented. The extracted noise spectral densities of desired noise sources will serve as a direct target for the verification of any proposed noise model developed.</p> <p>Fourth, new physics-based channel noise models to predict the channel noise, induced gate noise and their noise correlation are developed and verified with the extracted noise sources. The impact of the channel-length modulation (CLM) effect, the hot electron effect, and the velocity saturation effect on the desired noise sources in the deep sub-micron MOSFETs are discussed in detail.</p> <p>Lastly, the design strategies of a low noise amplifier based on the developed noise models and extracted noise information are presented as a guide line to choose the device size and bias condition of the transistors. The impact of the model accuracy on the simulated noise performance of a two stage low noise amplifier is also presented.</p> / Doctor of Philosophy (PhD)