The unabated continuation of the Moore's law has allowed the doubling of the number of transistors per unit area of a silicon die every 2 years or so. At the same time, an increasing demand on consumer electronics and computing equipments to run sophisticated applications has led to an unprecedented complexity of hardware designs. These factors have necessitated the abstraction level of design-entry of hardware systems to be raised beyond the Register-Transfer-Level (RTL) to Electronic System Level (ESL). However, power envelope on the designs due to packaging and other thermal limitations, and the energy envelope due to battery life-time considerations have also created a need for power/energy efficient design. The confluence of these two technological issues has created an urgent need for solving two problems: (i) How do we enable a power-aware design flow with a design entry point at the Electronic System Level? (ii) How do we enable power aware High Level Synthesis to automatically synthesize RTL implementation from ESL? This dissertation distinguishes itself by addressing the following two issues: (i) Since power/energy consumption of electronic systems largely depends on implementation details, and high-level models abstract away from such details, power/energy estimation at such levels has not been addressed thoroughly. (ii) A lot of work has been done in applying various techniques on control-data-flow graphs (CDFG) to find power/area/latency pareto points during behavioral synthesis. However, high level C-based functional models of various compute-intensive components, which could be easily synthesized as co-processors, have many opportunities to reduce power. Some of these savings opportunities are traditional such as clock-gating, operand-isolation etc. The exploration of alternate granularities of these techniques with target applications in mind, opens the door for traditional power reduction opportunities at the high-level. This work therefore concentrates on the aforementioned two areas of inadequacy of hardware design methodologies. Our proposed solutions include utilizing ESL simulation traces and mapping those to lower abstraction levels for power estimation, derivation of statistical power models using regression based learning for power estimation at early design stages, etc. On the HLS front, techniques that insert the power saving features during the synthesis process using exploration of granularity and scope of clock-gating, sequential clock-gating are proposed. Finally, this work shows how to marry two domains, that is estimation and reduction. In this regard, a power model is proposed, which helps in predicting power savings obtained using clock-gating and further guiding HLS to selectively insert clock-gating. / Ph. D.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-05-04T22:06:03Z No. of bitstreams: 1 HELDER FERNANDO DE ARAÚJO OLIVEIRA - TESE PPGCC 2015..pdf: 1535968 bytes, checksum: ea0ac08d16d7773542f5d7193c85c162 (MD5) / Made available in DSpace on 2018-05-04T22:06:03Z (GMT). No. of bitstreams: 1 HELDER FERNANDO DE ARAÚJO OLIVEIRA - TESE PPGCC 2015..pdf: 1535968 bytes, checksum: ea0ac08d16d7773542f5d7193c85c162 (MD5) Previous issue date: 2015-11-10 / Capes / Consumo de energia é um grande desafio durante o projeto de um SoC (System-on-a-Chip). Dependendo do projeto, para garantir maior precisão na estimação do consumo de energia, pode ser necessário estimar o consumo de energia do sistema ou parte dele utilizando diferentes elementos: diferentes abordagens de estimação, ferramentas ou, até mesmo, modelos descritos em variadas linguagens e/ou níveis de abstração. Porém, consiste em um desafio incorporar tais elementos para criação de um ambiente de simulação distribuído e heterogêneo, o qual permita que estes se comuniquem e troquem informações de modo sincronizado. Diante do exposto, a presente pesquisa tem como objetivo desenvolver uma abordagem, utilizando-se High Level Architecture (HLA), a fim de permitir a criação de um ambiente de simulação distribuído e heterogêneo, composto por diferentes ferramentas e modelos. Estes modelos podem ser descritos em diversas linguagens e/ou níveis de abstração, como também podem utilizar diferentes abordagens a estimação do consumo de energia. O uso da HLA permite que os elementos que compõem este ambiente heterogêneo possam ser simulados de maneira sincronizada e distribuída. A abordagem deve proporcionar a coleta e o agrupamento de dados de estimação de consumo de energia de modo centralizado. Para realização dos estudos de caso, foi utilizado um benchmark composto por um conjunto escalável de MPSoC (MultiProcessor System-on-Chip) descrito em C++/SystemC e o arcabouço Ptolemy. Um projeto em SystemVerilog/Verilog também foi utilizado para validar a coleta de dados de estimação de consumo de energia de modelos descritos nessas linguagens, por meio da abordagem proposta. Resultados experimentais demonstraram a flexibilidade da abordagem e sua aplicabilidade para a criação de um ambiente de simulação síncrono e heterogêneo, o qual promove uma visão integrada dos dados de energia estimados. / Energy consumption is a big challenge in SoC (System-on-a-Chip) design. Depending on the project requirements, to guarantee a better accuracy in power estimation, it might be necessary to estimate the power consumption of a system or part of it using different elements: different power estimation approaches, tools or, even, models described in different languages and/or abstraction levels. However, it is a challenge to incorporate these elements to create a simulation environment distributed and heterogeneous, which allows these elements to communicate and exchange information synchronously. In view of what has been exposed, the present research aims to develop an approach using HLA (High Level Architecture), enabling the creation of an environment distributed and heterogeneous, composed by different tools and models. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, it has been used a benchmark composed of a scalable set of MPSoCs (MultiProcessor Systemon-Chip) which is described in C++/SystemC and the Ptolemy framework. A project in SystemVerilog/Verilog was also used to validate the power estimation data collected from models described in these languages, through the proposed approach. The experimental results show the approach flexibility and its applicability on creation of a distributed and synchronous simulation environment, which promotes an integrated view of power estimation data.