published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

Correlated double sampling (CDS) is a widely used signal processing technique for removal of the Nyquist (reset) noise which is associated with charge sensing circuits employed in a solid state imager. In this thesis work, the power spectral density at the output of a correlated double sampling circuit with first-order low-pass filtered white noise at the input is calculated. A circuit constructed with discrete elements is made to simulate the output stage of a charge-coupled device (CCD). A low-pass filtered wide-band noise from a noise generator is added to the reset reference level when the output signal from this simulator is sampled by the correlated double sampling technique. The experiment measurements show that only about 10% of the noise power measured by simple sampling is obtained when CDS is employed. An autoregressive (AR) model is assumed to fit the sampled data and a recursive algorithm, based on least-squares solutions for the AR parameters using forward and backward linear prediction, is adopted for spectrum estimation. Some conclusions on choosing the bandwidth of the low pass filter for optimum operation is also included.

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The present paper introduces one very efficient and flexible time-domain analysis technique to predict the kinds of reflections and crosstalk. Numerical results show that this technique is indeed efficient and accurate in the transient analysis of a general multiple line system. Furthermore, this algorithm can be eventually coded in a form of a subroutine compatible with any standard CAD program, such as SPICE.

M.Ing. / In this investigation charge balancing will be investigated from an Electro-Magnetic- Compatibility perspective. The primary sources of common mode Electro-Magnetic- Interference in switching converters are the switching nodes. This is mainly due to the parasitic capacitance between the switching node and the reference earth. Filtering components that are currently used take up a lot of valuable space resulting in the products overall size and cost to increase. Combating common mode current at the source will drastically reduce the size or the need for these large filters. This investigation will focus on a simple method of reducing common mode noise (produced by the switching node), of a two wire system, at the source by making use of a compensating winding which requires very little or no additional space; a buck converter will be used to illustrate the concept. The investigation will start with an overview of Electro-Magnetic-Interference and its components (common and differential mode noise). This investigation will deal with the measurement of common and differential mode noise as well as general Electro-Magnetic-Interference measurement. A design of the buck converter and its drive circuit will also be presented. Reducing the common mode noise by making use of charge balancing using planar inductors will then be presented. This investigation contains the theoretical analysis as well as experimental results to validate the theory. The experiments show encouraging results in using this technique to minimise common mode noise in switched-mode-power-supplies.

Graduation date: 1996

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A new method for solving jitter noise in estimating high frequency waveform is proposed. It reduces the bias of the estimation in those points where all the other methods fail to achieve. It provides preliminary models for estimating percentiles in Normal, Exponential probability density function. Based on the model for Normal probability density function, a model for any probability density function is derived. The resulting percentiles, in turn, are used as estimates for the amplitude of the waveform. Simulation results show us with satisfactory accuracy.

This thesis examines substrate noise coupling for NMOS transistors in heavily doped substrates. The study begins with the analysis of an NMOS transistor switching noise in a digital inverter at the device level. A resistive substrate network for the NMOS transistor is proposed and verified. Coupling between N+- P+ contacts is compared both qualitatively and quantitatively with simulations. The difference between the N-P and P-P coupling is in the cross-coupling parameter. A new N-P model, which requires only five parameters, is proposed by taking advantage of an existing P-P model combined with the concept of a virtual separation. This model has been validated up to 2GHz with Medici simulations. The virtual separation concept has been validated with 2D/3D simulations and measurements from test structures fabricated in a 0.35μm TSMC CMOS heavily doped process. This model is useful when transistor switching noise is the dominant source of substrate noise. Applications of the new N-P model are demonstrated with circuit simulations. / Graduation date: 2004