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The objective of this research is to develop and implement a method for fault simulation that considers bridging faults in CMOS circuits that are tested using supply current monitoring. The discussion is restricted to single fault detection in CMOS combinational circuits. A CMOS circuit is represented by a two-level hierarchy. At the higher level, the circuit is partitioned into modules based on the circuit layout. Each module is represented at the lower level by a switch-level graph. This representation has the advantage of structural accuracy at the lower level and efficient logic propagation at the higher level. Based on a module's switch-level graph, an exhaustive list of bridging faults corresponding to certain physical defects can be derived. Fault collapsing techniques are used to optimize the exhaustive fault list. There are two major processes in this bridging fault simulation program, logic simulation and fault sensitization at switch level. The simulation program uses preprocessing and bit-wise parallelism to minimize computation time. At the end of fault simulation, a fault coverage and fault matrices suitable for test grading and fault diagnosis are produced for each test set. This research also identifies types of CMOS modules and uses them to analyze test generation for bridging faults. The completeness and minimality of switch-level test sets are considered for general series-parallel (GSP) modules. Finally, several single-module circuits are simulated using gate-level, switch-level and random test sets, and their effectiveness is compared. / Master of Science

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A study has been carried out to investigate the use of "real-time" radiography as a method of automated inspection of through-hole electronic circuit board solder joints. By evaluating five major solder defects it has been found that film radiography employing high contrast film results in a definite distinction between a good solder joint and a defective solder joint. The same five defects were also found to be distinguishable from a good solder joint when evaluated by a real-time radiographic inspection unit using digital image processing. Although the type of defect being investigated was not discernible, the ability to distinguish a good solder joint from a defective solder joint is a major step in the implementation of automated solder joint inspection for military electronics.

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The capability of measuring surface temperatures of hybrid circuits at the Virginia Tech Hybrid Microelectronics Laboratory has been established. This capability provides a quantitative method for effectively evaluating thermal design software. Surface operating temperatures were measured and predicted for an operating hybrid circuit. The temperatures were measured using an infrared thermal imaging system, which measures surface temperatures by detecting the infrared radiation emitted and reflected. The accuracy of the measurements has been quantified for variations in surface emissivity, convective cooling condition, and operating temperature range. The most accurate temperature measurement of a one-resistor circuit was compared to the operating temperature predicted by a lumped-parameter one-dimensional heat transfer analysis. The comparison agreed within the expected limits for this simple analysis and identified areas for possible improvement both of the model and the experimental technique. Thermal design of a circuit is critical because excessive temperatures are a common cause of circuit failure. Circuit designers rely on computer programs to predict circuit component temperatures because of the high cost of prototype experimentation. Accurate thermal design software that is currently available is too complicated for occasional use by circuit designers. Simple, yet accurate, thermal design software is essential for this type of design, so that circuit layouts can be quickly and easily optimized. / M.S.

On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals with cost-effective BIST methods and Test Pattern Generation (TPG) schemes in BIST for fault detection and diagnosis of analog circuits. Fault-based testing is used in analog domain due to the applicable test methods/ techniques being general and cost-effective. We propose a novel test method causing the Device Under Test (DUT) to saturate or get out of saturation to detect a fault with simple detection hardware. The proposed test method is best suited for use of existing building blocks in Systems-on-Chip (SoC) for implementation of an on-chip test signal generator and test response analyzer. Test generation for a fault in analog circuit is a compute intensive task. A good test generator produces a highly compact test set with less computational effort without trading the fault coverage. In this context, three new test generation methods viz., MultiDetect, ExpoTan, and MultiDiag for testing analog circuits are presented in this thesis. Testing of analog blocks based on circuit transfer function makes the proposed ATPG methods as general-purpose methods for all kinds of LTI circuits. The principle of MultiDetect method, (i.e., selecting a test signal for which the output amplitude difference between good and faulty circuits is minimum when compared to other test signals in an initial test set), helps in the generation of high quality compacted test set with less fault simulations. The experimental results show that the testing of LTI circuits using MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time. The generated test set with MultiDetect method can effectively detect both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as Built In Self Test (BIST). Test generation for a list of faults and test set compaction are two different phases in an ATPG process. To build an efficient ATPG, these two phases need to be combined with a technique such that the generated test set is highly compact and efficient with less fault simulations. In this context, a novel test set selection technique known as ExpoTan for testing Linear Time Invariant (LTI) circuits is also presented in this thesis. The test generation problem is formulated with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. Identification of a sinusoid that detects more faults results in an optimized test signal set. Fault diagnosis and fault location in analog circuits are of fundamental importance for design validation and prototype characterization in order to improve yield through design modification. In this context, we propose a procedure viz., MultiDiag for generation of a test set for analog fault diagnosis. The analog test generation methods, viz., Max, Rand, and MultiDetect etc., which are based on sensitivity analysis, may fail at times to identify a test signal for locating a fault; because the search for a test signal using these test generation methods is restricted to the limited test signals set. But, the MultiDiag method definitely identifies a test signal, if one exists, for locating a fault.