This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case) and 125 times faster (worst case). The accuracy of the model depends on the accurate evaluation of the non-linear transfer function from the various noisy nodes to the output. By modeling the noise transfer function of the circuit as closely as possible, 100% accuracy for the behavioral noise simulations compared with the HSPICE noise simulations is obtained. The macro model is written for a charge-pump phase-locked loop, but can be easily extended to other architectures. The simulations are completed using SpectreS in Cadence. The designer can use the model to estimate the jitter at the output of the PLL in a top-down design methodology or cross verify the performance of an existing chip in a bottom-up approach. / Graduation date: 2001