The classical front end analysis in speech recognition is a spectral analysis which parametrizes the speech signal into feature vectors; the most popular set of them is the Mel Frequency Cepstral Coefficients (MFCC). They are based on a standard power spectrum estimate which is first subjected to a log-based transform of the frequency axis (mel- frequency scale), and then decorrelated by using a modified discrete cosine transform. Following a focused introduction on speech production, perception and analysis, this paper gives a study of the implementation of a speech generative model; whereby the speech is synthesized and recovered back from its MFCC representations. The work has been developed into two steps: first, the computation of the MFCC vectors from the source speech files by using HTK Software; and second, the implementation of the generative model in itself, which, actually, represents the conversion chain from HTK-generated MFCC vectors to speech reconstruction. In order to know the goodness of the speech coding into feature vectors and to evaluate the generative model, the spectral distance between the original speech signal and the one produced from the MFCC vectors has been computed. For that, spectral models based on Linear Prediction Coding (LPC) analysis have been used. During the implementation of the generative model some results have been obtained in terms of the reconstruction of the spectral representation and the quality of the synthesized speech.

Cryptographic algorithms, like the Advanced Encryption Standard, are frequently used in todays electronic appliances. Battery operated devices are increasingly popular, creating a demand for low energy solutions. As a microcontroller is incorporated in virtually all electronic appliances, the main objective in this thesis is to evaluate possible hardware implementations of AES and implement a solution optimized for low energy consumption, suited for incorporation in a microcontroller. A good cost/performance balance is also a design goal. An existing solution based on a 32 bit architecture with support for 128 bit keys was chosen as a basis and altered in order to lower area and energy consumption. The alterations yielded a 13.6% area reduction as well as 14.2% and 3.9% reduction in energy consumption in encryption and decryption mode, respectively. In addition to alterations in the datapath, low energy techniques like clock gating and numerical strength reduction has been applied in order to further lower the energy consumption. The proposed architecture was also extended in order to accommodate 256 bit keys. Although this increased the area by 9.2%, the power consumption was still reduced by 7.6% and 1.3% in en- and decryption, compared to the architecture chosen as basis. As AES is an algorithm which easily can be parallelized, a high throughput solution utilizing a 128 bit datapath was implemented. This AES module is able to process 372.4 Mbps at an operating frequency of 32 Mhz and is based on the same architecture as the 32 bit datapath solution. In addition, this implementation yielded excellent energy per encryption figures, 24.5% lower than the 32 bit solution. The alternative to performing AES in a dedicated hardware module is to perform it using software. In order to have a basis for comparison, a software solution optimized for 32 bit architectures was implemented. Simulations show that the energy consumption attained when performing AES in the proposed hardware module is approximately 2.3% of what a software solution would use. In addition, the throughput is increased by a factor of 25. The architecture proposed in this thesis combines relatively high throughput with modest demands to area and low energy per encryption.

Lidar is an optical remote sensing technology which uses the backscattered light to create information profiles of the scanning area. Normally the air is used as propagation medium, but in this work the Lidar's efficiency to detect submerged target in water is discussed.   Following the theories of light propagation in the air and in the water a model to simulate the target detection is created. The values of scattering and absorption of the laser pulse in water are estimated by Morel equations which give accurate values of the sea water properties. Scattering and absorption define the optical properties of the medium, so the attenuation and the backscattering coefficient are calculated. These value will have a strong dependency to the salinity, pressure, temperature, sea water constituents and so on.   After the estimation of the parameters a model based on Lidar Equation, Fresnel Equations and Snell´s law has been developed with the aim of predict the maximum range to detect the sea surface and the maximum depth to detect the sea bottom.     In order to verify the goodness of the model, a prototype 532nm Lidar system has been used to collect experimental data. The Lidar was used from a 50m high building scanning from near vertical incidence to near horizontal incidence.   The extracted data from the simulations have been compared with the data obtained from realized test. This has given  us a predicted maximum range to detect the sea surface of 220m and an estimated  maximum depth for a reference target of 17m.

This report describes the assessment and design of a 10 dBm 2.4 GHz CMOS PA including driver stage. The PA is designed in a 0.18 um CMOS technology. A three stage PA has been designed due to the high voltage gain needed. Class F has been chosen for the output stage. An output filter short-circuiting the second harmonic frequency and reflecting the third harmonic frequency is used to obtain the near-square drain voltage that is characteristic to class F. A lowered supply voltage of 0.9 V is used to avoid exceeding the transistor break-down voltage of 2 V. The typical output power achieved is 10.2 dBm. The drain efficiency of the output stage is 47.7 %, and the PAE of the entire PA is 30.5 %. The final layout excluding bonding pads consumes an area of 0.66 mm2, including four internal inductors consuming a total of 0.59 mm2. The PAE obtained is higher than those of a selection of recently published PAs that are comparable in technology, frequency and output power.

This paper reports on the modeling and simulation of a continuous-time delta-sigma analog to digital converter (ADC) in VHDL AMS. The ADC is intended for use in a microcontroller and is therefore underlying restrictions on power consumption. Continuous-time delta-sigma architectures are well known for their good low-power capabilities compared to discrete-time realizations. This is due to their reduced demands to the gain bandwidth product (GBW) of the internal amplifiers in the ADCs. Continuous-time ADCs often operate with GBWs in the range of the sampling frequency, fs. The ADC presented in this work is also employing a previously reported compensation technique which ideally allows the GBW to be reduced further >20 times of this. Considering that the current drain in the amplifiers usually is proportional with GBW, this could be a promising power saving technique. The work focuses on the development of two similar models of a 2-order continuous-time delta-sigma ADC in VHDL-AMS, where one of the ADCs is using the compensation technique. The main purpose is to see how the compensated ADC is affected by nonidealities such as GBW-variation, finite amplifier gain, RC-product variation, excess loop delay and finite DAC slew rate compared to the performance of the noncompensated ADC. The required accuracy for the modeled ADCs is 62dB Signal to Noise and Distortion Ratio (SNDR), thus an appropriate oversampling ratio (OSR) also must be found. The simulations show that the compensated ADC has similar performance as the noncompensated ADC operating with GBW=10*fs when subject to the different nonidealities. With an OSR=64 it stays within the accuracy specification for GBWs >= 0.05*fs This is however only valid if actual GBW stays within +-40% of the GBW compensated for. For larger deviations, especially lower GBW values, the SNDR drops rapidly. It is also shown that the internal signal swing in the ADC is reduced for low GBW values. This may limit the practical achievable SNDR when subject to circuit noise. If these potential drawbacks are circumvented, the compensation technique could lead to a further decrease of the power consumption in continuous-time delta-sigma ADCs.

The goal of this Master Thesis is to study shared radio resources among users with different services requirements. The analyzed properties of the wireless connection are fairness, throughput and delay for users demanding different services and QoS requirements. Four scheduling algorithms are used for allocating system resources. Two of them, Max Rate and Round Robin, are used as references to analyze throughput and fairness respectively. The other two algorithms, Proportional Fair Scheduling and Rate Craving Greedy, exploit the idea of multiuser diversity improving the throughput without comprising fairness. Different fading radio channel models are investigated, but only urban environments and pedestrian users are simulated in this report. OFDM has been the technique used to transmit signals over the wireless channel. The performance of these algorithms is analyzed and compared through MATLAB computer simulations.

A 64-modulus prescaler operating at 5.8 GHz has been designed in a 0.18 μm CMOS process. The prescaler uses a four-phase high-speed ÷4 circuit at the input, composed of two identical cascaded ÷2 circuits implemented in pseudo-NMOS. The high-speed divider is followed by a two-bits phase switching stage, which together with the input divider forms a ÷4/5/6/7 circuit. The phase switching stage is mostly implemented in complementary CMOS. After this follows four identical ÷2/3 cells with local feedback, also implemented in complementary CMOS. Other architectural approaches are also described and tried out. An architecture based solely the ÷2/3 cells with local feedback is presented. The ÷2/3 cells were implemented and simulated, and worked up to 2.3 GHz. An alternative high-speed divider based on an inverter ring interrupted by transmission gates is also described. Simulations showed that a divider using pseudo-NMOS inverters and CMOS transmission gates operated well and gave out four signals evenly spaced in phase at a input frequency of 4.8 GHz.

Software defined radio (SDR) is an emerging trend of radio technology. The idea is basically to move software as close to the antenna of a radio system as possible, to improve flexibility, adaptability and time-to-market. This thesis covers the description of a DSP architecture especially optimized for modulation / demodulation algorithms of low-complexity, low-power radio standards. The DSP allows software processing of these algorithms, making SDR possible. To make the DSP competitive to traditional ASIC modems, tough constraints are given for area and power consumption. Estimates done to indicate the power consumption, area and computational power of the DSP, shows that a software implementation of the studied physical layer should be possible within the given constraints.

This work investigates whether in vivo magnetic resonance spectroscopy (MRS) and diffusion-weighted magnetic resonance imaging (DW-MRI) can be used for non-invasive monitoring of treatment response in an experimental tumor model. Twenty-nine nude mice with colorectal adenocarcinoma HT29 xenografts on each flank were included into 2 separate experiments. In the first experiment control tumors were compared to tumors irradiated with 15 Gy at Day 2. MR baseline values were established at Day 1 followed by 4 post-treatment MR examinations. Mice were sacrificed for histological response evaluation and high-resolution ex vivo magic angle spinning (HR-MAS) MRS of tumor tissue samples for correlation with in vivo MR data. The second experiment included 3 groups recieving combined chemoradiation therapy; Control group, Capecitabine (359 mg/kg daily Day 1 - Day 5) group and Capecitabine (359 mg/kg daily Day 1 - Day 5) + Oxaliplatin (10 mg/kg at Day 2) group. All left-sided tumors were irradiated with 15 Gy at Day 2. Three repeated MR examinations were compared to the MR baseline values established at Day 1. After MR examinations the mice were sacrificed for histological response evaluation. The choice of chemoterapy was based on a clinical patient study currently running at Rikshospitalet-Radiumhospitalet HF, the LARC-RRP (Locally Advanced Rectal Cancer - Radiation Response Prediction) study. In Experiment 1, localized 1H MR spectra were acquired at short (35 ms) and long (144 ms) echo times (TEs) using a single-voxel technique. The metabolite choline is related to tumor growth. The choline peak area relative to the unsuppressed 35 ms TE water area in the same voxel, i.e. the normalized choline ratio, was assessed in all MRS examinations. For both TEs, the choline ratio increased after irradiation, followed by a decrease and a renewed increase 12 days after irradiation. In Experiment 1, statistically significant differences at the 0.1 level were observed between the choline ratios at Day 5 and Day 12 (p = 0.068) for short TE and between the ratios at Day 3 and Day 8 (p = 0.05) for long TE. The change in choline ratio was in accordance with the tumor necrotic fraction (NF) found in histological analyses. Principal component analysis (PCA) revealed a correlation between the score values of ex vivo HR-MAS MR spectra and necrosis. This suggests a correlation between ex vivo and in vivo MRS. In both experiments, the diffusion in the HT29 xenografts varied during treatment. There was a correlation between the amount of necrosis in tumor and the calculated apparent diffusion coefficient (ADC) obtained from DW-MRI examinations. In Experiment 1, statistically significant differences at the 0.1 level were observed between the ADCs at Day 3 and Day 5 (p = 0.05), between Day 5 and Day 12 (p = 0.068), and between Day 8 and Day 12 (p = 0.068). The HT29 xenografts responded to treatment with an initial increase of necrosis due to the short-term effect of treatment, stimulating development of fibrosis. In accordance to the change in choline and ADC, the level of necrosis increased 8 - 12 days after start of treatment, which might correspond to the long-term effect of treatment. The findings in this work shows that in vivo MRS and DW-MRI can be used for non-invasive monitoring of treatment response in an experimental tumor model. This suggests that in vivo MRS and DW-MRI could yield important information about a tumors response to therapy.

This thesis is divided into two parts, the design of a practical first order open loop sigma-delta modu- lator using discrete components, and simulation of a third order OLSD ADC to investigate the consequences of circuit imperfections - and determining circuit requirements if the ADC should be used in a GSM system. The practical modulator is designed as a first order OLSD ADC, with standard discrete components such as operational amplifiers and switches, and a microcontroller with a built in ADC. The practical circuit uses surface mount capacitors with a tolerance of 20%, resulting in poor matching and inaccurate behavior of the modulo integrator. Despite the poor matching, the OLSD ADC shows a distinct noise shaping, with a slope of about 20dB per decade. The quantization noise is not the dominating noise source in the circuit, and the quantizer resolution must to be set to four bits or less to achieve any improvement in performance over the standard ADC. The third order modulator is modeled and simulated at a behavior level using VHDL-AMS. The ideal circuit confirms the results from the preliminary project [12], where the quantizer resolution had to be equal to or larger than the modulator order to obtain proper noise shaping. The simulations shows that the ideal third order modulator with a four bit quantizer can achieve a SNR of 88:51dB, and an ENOB of 13:78bits within a 200kHz band. The third order modulator is simulated with circuit imperfections to determine the effect of these when there is no feedback present. Introducing finite gain in the integrators results in harmonic distortion at the output. This harmonic distortion is a result of leakage of the internal reset signal in the integrators. By setting the gain in all three integrators to 2OSR = 42dB, the SNR of the third order modulator sinks to 71:74dB. The gain in the ¯rst integrator is increased to 60dB, and the SNR raises to 84:52dB. The first integrator is the most crucial to the performance of the modulator, as is the case for conventional sigma-delta ADCs. The circuit is also simulated with capacitance mismatch and comparator o®set in the modulo integrator. These two imperfections results in the same error - the output voltage from the integrator di®ers from the ideal case. Simulations show that the total voltage error should be significantly less than 0.5VLSB to obtain the noise shaping. If the integrator output error is too large, the noise shaping will totally disappear. In general, it has been proved that the OLSD modulator with modulo integrators works as intended, the quantization noise is shaped like in conventional sigma-delta modulators. The modulator is very sensitive to capacitor mismatch and parasitics. The e®ect of these capacitor imperfections will increase as the quantizer resolution increase, because the error will cover more units of VLSB. It is important to minimize these capacitor effects, as increased quantizer resolution will allow a greater input signal swing.