In this thesis the optimal transmission rate in ad hoc wireless networks is analyzed. The performance metric used in the analysis is probability of outage. In our system model, users/packets arrive randomly in space and time according to a Poisson point process, and are thereby transmitted to their intended destinations using either ALOHA or CSMA as the MAC protocol. Our model is based on an SINR requirement, i.e., the received SINR must be above some predetermined threshold value, for the whole duration of a packet, in order for the transmission to be considered successful. If this is not the case an outage has occurred. In order to analyze how the transmission rate affects the probability of outage, we assume packets of K bits, and let the packet duration, T, vary. The nodes in the network then transmit packets with a requested transmission rate of Rreq=K/T bits per second. We incorporate transmission rate into already existing lower bounds on the probability of outage of ALOHA and CSMA, and use these expressions to find the optimal packet duration that minimizes the probability of outage. For the ALOHA protocol, we derive an analytic expression for the optimal spectral efficiency of the network as a function of path loss, which is used to find the optimal packet duration Topt . For the CSMA protocol, the optimal packet duration is observed through simulations. We find that in order to minimize the probability of outage in our network, we should choose our system parameters such that our requested transmission rate divided by system bandwidth is equal to the optimal spectral efficiency of our network.

High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques. A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%. The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%.

To make a double CubeSat with limited power resources capable of transmitting large amounts of data to Earth a high gain antenna is needed. In this thesis a switched beam MSA array operating at 5.84 GHz has been designed to operate on a double CubeSat. The array has 5 beams and uses a switched-line phase shifter to switch between beams. Three different array geometries has been proposed. Computer simulations suggest that the array should be capable of an effective beamwidth of over 60 degrees with a directivity of over 11 dBi. A feed network has been designed to fit the best suited geometry. A ground plane will separate the feed network from the antenna elements. Along with the full array solution all the sub parts has been realized as test circuits. This allows for an evaluation of their characteristics. A TRL calibration kit has also been designed so that the sub parts could be more accurately evaluated. When sending the circuits to fabrication it appeared to be a problem with the selected substrate used for the antenna elements. A redesign using the same substrate for the feed network and antennas was done and production commenced. As it turns out, the TRL calibration kit was not good enough so the S-parameters had to be measured with regular SOLT calibration. Significant problems with connection to ground and mismatches due to a poor SMA-to-microstrip transition was encountered. This caused large deviations between measured and simulated results. It was also discovered that the wrong dielectric constant had been used. This error caused the antenna elements to be dimensioned for operation at 5.70 GHz instead of 5.84 GHz. Problems was also encountered in the switched line phase shifter design. Beam-lead PIN-diodes has been used and due to their small size, a sufficient quality of the soldering was not achieved. This lead to different losses through the phase shifter which again caused the different beam directions to vary from simulations. Only one beam had characteristics similar to simulations. Measurements on the array without phase shifters showed good correspondence with simulation results (adjusted for the correct dielectric constant). It is concluded that by making a better SMA-to-microstrip transition, improve the soldering work and do a redesign with the correct dielectric constant, the array configuration should work as outlined in the design process.

In this thesis a compact drain current model for nanoscale double-gate MOSFETs is presented. The model covers all operation regimes and bias voltages up to 0.4V. The modeling is done using conformal mapping techniques to solve the 2D Laplace equation in sub-threshold, and using a long channel model in strong-inversion. In near threshold, a quasi-Fermi level model which uses empirical constants is used to find the current. A continuous model is found by expressing asymptotes in the sub-threshold and strong inversion regimes, and combining them using a interpolation function. The interpolation function uses a parameter that is decided analytically from the near threshold calculations. The model shows good agreement with numerical simulations for bias voltages below 0.4V and channel lengths bellow 50nm.

Digital multipliers are an important part of most of digital computation systems, such as microcontrollers and microprocessors. Multiplication operation is a quite complex task, thus there is many different solution varying in area, speed and power consumption. An important notice is that multipliers often are a part of critical path of a system which makes them especially important for these factors. During last decade, power efficiency has become an important issue in digital design and a lot of design methods has been created and investigated to meet this subject. It is a known fact that most of power consumed by arithmetic circuit is dissipated by hazards and toggles (up to 75%), that do not bring any information to final result. The method of evaluating the amount of spurious switching and its effect on power dissipation is investigated here. This thesis aims to find a method to estimate switching characteristics and its effect on power dissipation of eight supplied multipliers given in form of HDL net-list with some software overhead. As switching generally stands for majority of power consumption in digital CMOS circuits, this effect gives also good indication of overall power dissipation. One of the difficulties in estimating average power and transition density is pattern dependency problem. The method based on Monte Carlo technique is used where an adequate accuracy is obtained within moderate time and resource usage. Three of investigated multipliers are net-lists created by using methodology developed in [21]. These are synthesized and laid out in the technology used by Atmel Norway. The amount of logical state changes is compared from pre- and post- synthesis net-lists. The technology mapped net-lists are also examined for power consumption to see the connection between switching and dynamic power dissipation. The fan-out delay model used to estimate total toggling gives a good approximation of circuit properties; it is however too simple to give a good estimate of spurious toggling inside the circuit and its effect on power consumption. The same estimation technique is used to investigate a DesignWare circuit (DW02) which is an industrial approach of building fast and power efficient multipliers. The results show that this is the most power effective solution among the examined circuits (45-47% less than the most power efficient circuit from [21]) It is also a solution with smallest amount of hazards during a multiplication operation (38-52%). A circuit generated by module generation software (ModGen) is also investigated. This solution is quite power efficient, it has however largest amount of power dissipated by the spurious toggling (62-68%). It is also noticed that transition density and what follows the power dissipation in strongly dependent on the process, temperature and voltage variation. In fact the higher temperature gives reduction in power consumption.

Perfect lenses operating in the near visible spectrum has only recently been introduced, and these kind of metamaterials seem to have a large potential. One problem encountered with these perfect lenses are exceedingly large intrinsic losses, making them impractical for use in applications. This project has explored some of the limitations in using gain to compensate for these losses, specifically the effect of gain saturation has been considered. Gain saturation has been proven to limit the maximum parallel spatial frequency that can be reproduced by the lens. Even though, it has been shown that amplification has the potential to increase the resolution limit by a measurable factor. In the case of several waves traversing the lens simultanously, the critical factor is how much of the total amplitudes lies in waves close to the resolution limit. Waves with relatively small parallel spatial frequencies requires small amplifications, and those with high parallel spatial frequencies will get attenuated or reflected almost immediately, meaning both these types contribute little to gain saturation.

A precise subthreshold potential model for the Quadruple FET (QuadFET) is presented in this thesis. The attempt of modeling the FinFET ("Fin" FET) in the same way failed, but the procedure of the attempt will still be presented in this thesis, and a conclusion of why this modeling did not work is given. For the QuadFET, an analytical solution of the inter-electrode potential distribution of the double-gate MOSFET (DG MOSFET) is used by performing a simple geometric scaling transformation. This is done with a high degree of precision due to structural similarities between the QuadFET and DG MOSFET, accounting for the dierence in gate control of the two devices. A parabolic approximation is then used to model the the cut-plane in the middle of the device, perpendicular to the electron ow from source to drain, of the QuadFET. The resulting analytical solution agrees very well with numerical simulations. For the FinFET, the same analytical solution of the DG MOSFET is used directly in the ground plane of the device, assuming that the electric elds going through the ground plane, into the thick substrate, is negligible. Conformal mapping is then used in the same plane as modeled in the QuadFET, that is the plane in the middle of the device, perpendicular to the electron ow from source to drain, resulting in an analytical solution of the FinFET. Since the potential curvature in the source-drain direction was neglected when making the three dimensional problem of the FinFET to a two dimensional one, the modeling failed. However, an attempt of modeling the transistor has been tested, the electrostatics of the device is better known, and a new way of modeling the device is briey discussed.

More to come

Au catalyst ZnO nanostructures have been grown on the a- and c-plane sapphire substrate by PLD. Influence of substrate lattice orientation, substrate surface and different substrate annealing temperature have been characterized by AFM, SEM and XRD. This report shows that a-plane sapphire substrate annealed at 1000 degree C and 1200 degree C improves the growth condition of Au catalyst ZnO nanostructures. For c-plane sapphire; annealing at 1200 degree C and 1400 degree C enhances the nanostructure growth. The better growth condition is a result of the terrace-and-step morphology seen on the substrate surface prior to growth. This report also indicates a correlation between the azimuthal in-plane alignment of the grown nanostructures and the sapphire substrate lattice orientation.

The main goal of this thesis is to present two good alternatives for the HDL+ protocol proposed for ratification in STANAG 4538, as this partially is restricted by a patent claims. The HDL+ protocol is used as a starting point, and in order to accommodate for the patented parts, the adaptive process is altered, and the code combining process is removed for the highest rate. For simplifying the comparison between the performance of the proposed protocols, and the HDL+, both proposed protocols is simulated in a MATLAB environment, over the same channels as Harris has presented the throughput capabilities of the HDL+. These channels include the AWGN, single tap channel with flat fading, the ITU-MLD channel, and the ITU-MLD channel with Long- and Intermediate- Time SNR variations. By analyzing the results, it is clear that the current implementation of the proposed protocols does not achieve as high throughput as the HDL+, but there are indications that there is potential for better results if further development is performed.