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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

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Showing 1 to 2 of 2 (0.052 seconds)

Spelling suggestions: "subject:"elektronische atemsysteme"" "subject:"elektronischen atemsysteme""

1

Wireless Interconnect for Board and Chip Level

Fettweis, Gerhard P., ul Hassan, Najeeb, Landau, Lukas, Fischer, Erik 11 July 2013 (has links) (PDF)
Electronic systems of the future require a very high bandwidth communications infrastructure within the system. This way the massive amount of compute power which will be available can be inter-connected to realize future powerful advanced electronic systems. Today, electronic inter-connects between 3D chip-stacks, as well as intra-connects within 3D chip-stacks are approaching data rates of 100 Gbit/s soon. Hence, the question to be answered is how to efficiently design the communications infrastructure which will be within electronic systems. Within this paper approaches and results for building this infrastructure for future electronics are addressed.
Elektronische Systeme
Kommunikationsinfrastruktur
Sonderforschungsbereich 912
Hochadaptive Energieeffiziente Systeme
Electronic systems
communications infrastructure
Collaborative Research Centre 912
ddc:620
ddc:621.3
rvk:ZN 6420
2

Wireless Interconnect for Board and Chip Level

Fettweis, Gerhard P., ul Hassan, Najeeb, Landau, Lukas, Fischer, Erik January 2013 (has links)
Electronic systems of the future require a very high bandwidth communications infrastructure within the system. This way the massive amount of compute power which will be available can be inter-connected to realize future powerful advanced electronic systems. Today, electronic inter-connects between 3D chip-stacks, as well as intra-connects within 3D chip-stacks are approaching data rates of 100 Gbit/s soon. Hence, the question to be answered is how to efficiently design the communications infrastructure which will be within electronic systems. Within this paper approaches and results for building this infrastructure for future electronics are addressed.
info:eu-repo/classification/ddc/620
ddc:620
info:eu-repo/classification/ddc/621.3
ddc:621.3

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