Thesis (Ph. D.)--University of Washington, 2000. / Vita. Includes bibliographical references (p. 253-264).

A requirements analysis approach for addressing the functional requirements of embedded systems has been proposed. Also proposed is a design approach based on the concurrent object-oriented programming paradigm. The design approach takes a specification created using the requirements analysis approach and transforms it into a detailed design. The detailed design is implemented using ACf++, a concurrent C++ that derives its concurrency semantics from the Actor model. The two approaches are illustrated by a simple but representative process control problem. The requirements analysis approach in conjunction with the design approach provides a high level of traceability and promotes the reusability of specifications and design. Improved reliability and reduced development and maintenance costs also are potential benefits. Extensions of the work include an integrated software development environment for embedded systems. / Master of Science

Thesis (Ph. D.)--University of New South Wales, 2000. / Addenda sheet inserted. Includes bibliographic references. Also available online.

Thesis made openly available per email from author, August 2015.

Leung Cheung-chi. / "July 2004." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (p. 77-81). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Thesis (Ph.D.)--McMaster University, 2005. / Supervisor: Nicola Nicolici. Includes bibliographical references (189-208 p.)

The growth of applications for embedded processors has spawned a need for highly configurable devices. Custom microprocessors have long life cycles for a fast paced market, where as off-the-shelf designs often do not provide the level of configuration, nor the ability to allow system-on-chip designs. This paper presents a description for a software environment that allows designers to provide configuration options for a design, and responds by dynamically reconfiguring the environment to provide a ready to test design. A background survey is provided on current embedded RISC architectures, along with a proposed new embedded ISA and a cycle-level simulator. Justification is presented for a new instruction format to reduce code size with little loss to performance. A manual is also provided for the new ISA. / Graduation date: 2003

The AE32000 processor core, developed by Advanced Digital Chips Inc., Korea, is used primarily in the embedded processing environment. The AE32000 simulator models this embedded processor core having high code density. An enhanced simulator was developed to study the performance of the present Instruction Set Architecture after comparison with the Simplescalar ARM simulator. ARM is among the most widely used processor cores for embedded applications and so was chosen for this comparison. Code density of the AE32000 is very high because of its shorter instruction length. This results in a smaller footprint inside the memory. But the longer instruction length of the ARM proves better when it comes to performance. The LERI(Load Extension Register Immediate) unit of the AE32000 has a special role before instructions that need long immediate values during execution. / Graduation date: 2004

A new and improved stabilizer was developed for the variable speed generation (VSG) system. The VSG system exhibits periodic oscillations which sometimes leads to a loss of synchronism. After careful study, a simple but effective strategy to stabilize the system was implemented with real time digital feedback control. The VSG system consists of an engine, which is the prime mover, driving a doubly fed machine (DFM), which is the generator. The stator of the DFM is directly connected to the grid while the rotor is connected to the grid through a power electronic converter. The converter used in this study is a series resonance converter (SRC), but the proposed method may also be applied to other kinds of converters. The stabilizer senses the RPM of the engine, the feedback signal, and controls the rotor current amplitude and frequency of the doubly fed machine. Control was implemented using the 80C196KB microcontroller. The software consists of a mix of "C" and assembly language. Speed being an important factor in the implementation, care was taken to minimize the control loop times. The important features of the hardware and software developed for the stabilizer are: (1) 12 MHz controller board (2) Real time digital band pass filter (3) Instantaneous rotor speed measurement (4) Interrupt driven measurement and control loops (5) User defined setup parameters (6) IBM PC based real time serial communication The performance of the VSG system was studied with and without the stabilizer. A significant improvement in the stability of the system was noticed over the entire region of operation. / Graduation date: 1991

Action recognition had become prosperous in development and been broadly applied in several sectors. From homeland security, personal property, home caring, even the smart environment and the motion-sensing games, are in its territories This paper analysis the algorithm of Action recognition for embedded system, finds that there are many blocks can use the parallel execution to compute more efficiently. This paper tries to implement action recognition algorithm on Multiple-Streaming Multimedia Unit (MSMU). MSMU is a MMX-like SIMD architecture, with SIMD Operation and Data Storage. By introduction the concept of multiple streaming, MSMU will be able to modulate the amount of parallel data streams dynamically via switching the instruction mode. With Mode Switching and new added transfer instruction to compute 2D image processing, study the benefit of the instruction mode switching Through comparing the 128-bit SSE architecture and MSMU architecture with the practical example, highlight the problems that exploiting the subword parallelisms facing and bring out the advantage of Multistreaming. For the algorithm, study the slicing the minimum element and using the bitwise operation approach to better efficiency. Compare to embedded SIMD architecture "WMMX", MSMU can achieve 3.49¡Ñ overall speedup.