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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

A TDMA-MAC Protocol for a Seismic Telemetry-Network with Energy Constraints

Höller, Yvonne 10 1900 (has links)
ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / The requirements for a seismic telemetry-network are even more stringent than the well known problems of sensor networks. Existing medium access control (MAC) protocols suggest reducing energy consuming network activity by reducing costly transmissions and idle listening. Furthermore, it is required to set up communication patterns in different priority levels as well as ensuring fast handling of critical events. A protocol is proposed that operates with two parallel sets of time schedules in a time-division-multiple-access (TDMA) sense of periodic activity for listening and for transmitting. Synchronization packets sent from a central base station ensure optimal response times.
2

Dynamic Task Allocation in Robot Swarms with Limited Buffer and Energy Constraints

Mohan, Janani 26 April 2018 (has links)
Area exploration and information gathering are one of the fundamental problems in mobile robotics. Much of the current research in swarm robotics is aimed at developing practical solutions to this problem. Exploring large environments poses three main challenges. Firstly, there is the problem of limited connectivity among the robots. Secondly, each of the robots has a limited battery life which requires the robots to be recharged each time they are running out of charge. Lastly, the robots have limited memory to store data. In this work, we mainly focus on the memory and energy constraints of the robot swarm. The memory constraint forces the robots to travel to a centralized data collection center called sink, to deposit data each time their memory is full. The energy constraint forces the robots to travel to the charging station called dock to recharge when their battery level is low. However, this navigation plan is inefficient in terms of energy and time. There is additional energy dissipation in depositing data at the centralized sink. Moreover, ample amount of time is spent in traveling from one end of the arena to the sink owing to the memory constraint. The goal is that the robots perform data gathering in the least time possible with the optimal use of energy. Both the energy and time spent while depositing data at the sink act as an additional overhead cost to this goal. In this work, we propose to study an algorithm to tackle this scenario in a decentralized manner. We implement a dynamic task allocation algorithm which accomplishes the goal of exploration with data gathering by assigning roles to robots based on their memory buffer and energy levels. The algorithm assigns two sets of roles, to the entire group of robots, namely: Role A is the data gatherer, a robot which does the task of workspace exploration and data gathering, and Role B is data relayer, a robot which does the task of data transportation from data gatherers to the sink. By this division of labor, the robots dynamically decide which role to choose given the contradicting goals of maximizing data gathering and minimizing energy loss. The choice of a robot to perform the task of data gathering or data relaying is the key problem tackled in this work. We study the performance of the algorithm in terms of task distribution, time spent by the robots on each task and data throughput. We analyze the behavior of the robot swarm by varying the energy constraints, timeout parameter as well as strategies for relayer choice. We also test whether the algorithm is scalable.
3

Software Synthesis for Energy-Constrained Hard Real-Time Embedded Systems

TAVARES, Eduardo Antônio Guimarães 31 January 2009 (has links)
Made available in DSpace on 2014-06-12T15:49:47Z (GMT). No. of bitstreams: 1 license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2009 / A grande expansão do mercado de dispositivos digitais tem forçado empresas desenvolvedoras de sistemas embarcados em lidar com diversos desafios para prover sistemas complexos nesse nicho de mercado. Um dos desafios prominentes está relacionado ao consumo de energia, principalmente, devido aos seguintes fatores: (i) mobilidade; (ii) problemas ambientais; e (iii) o custo da energia. Como consequência, consideráveis esforços de pesquisa têm sido dedicados para a criação de técnicas voltadas para aumentar a economia de energia. Na última década, diversas técnicas foram desenvolvidas para reduzir o consumo de energia em sistemas embarcados. Muitos métodos lidam com gerenciamento dinâmico de energia (DPM), como, por exemplo, dynamic voltage scaling (DVS), cooperativamente com sistemas operacionais especializados, a fim de controlar o consumo de energia durante a execução do sistema. Entretanto, apesar da disponibilidade de muitos métodos de redução de consumo de energia, diversas questões estão em aberto, principalmente, no contexto de sistemas de tempo real crítico. Este trabalho propõe um método de síntese de software, o qual leva em consideração relação entre tarefas, overheads, restrições temporais e de energia. O método é composto por diversas atividades, as quais incluem: (i) medição; (ii) especificação; (iii) modelagem formal; (vi) escalonamento; e (v) geração de código. O método também é centrado no formalismo redes de Petri, o qual define uma base para geração precisa de escalas em tempo de projeto, adotando DVS para reduzir o consumo de energia. A partir de uma escala viável, um código customizado é gerado satisfazendo as restrições especificadas, e, dessa forma, garantindo previsibilidade em tempo de execução. Para lidar com a natureza estática das escalas geradas em tempo de projeto, um escalonador simples em tempo de execução é também proposto para melhorar o consumo de energia durante a execução do sistema. Diversos experimentos foram conduzidos, os quais demonstram a viabilidade da abordagem proposta para satisfazer restrições críticas de tempo e energia. Adicionalmente, um conjunto integrado de ferramentas foram desenvolvidas para automatizar algumas atividades do método de síntese de software proposto
4

Scheduling hard real-time tasks in heterogeneous multiprocessor platforms subject to energy and temperature constraints / Agendando tarefas duras em tempo real em plataformas de multiprocessadores heterogêneas sujeitas a restrições de energia e temperatura

Valentin, Eduardo Bezerra, 92-36710870 29 September 2017 (has links)
Submitted by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2018-02-08T12:48:35Z No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_Eduardo Bezerra Valetim.pdf: 1753904 bytes, checksum: b47b056ce4f5f67a30051e12c578323a (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2018-02-08T12:49:13Z (GMT) No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_Eduardo Bezerra Valetim.pdf: 1753904 bytes, checksum: b47b056ce4f5f67a30051e12c578323a (MD5) / Made available in DSpace on 2018-02-08T12:49:13Z (GMT). No. of bitstreams: 2 license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) Tese_Eduardo Bezerra Valetim.pdf: 1753904 bytes, checksum: b47b056ce4f5f67a30051e12c578323a (MD5) Previous issue date: 2017-09-29 / The power wall is a barrier to improvement in the processor design process due to the power consumption of components. The production of energy optimum systems demands knowledge of different disciplines. The usage of heterogeneous multicore platforms is appealing for recent applications, e.g., hard real-time systems. The motivation is the potential reduced energy consumption offered by such platforms. Hard real-time systems are present in life critical environments. Reducing the energy consumption on such systems is an onerous process. Scheduling becomes particularly challenging to improve system utilization and minimize system energy consumption and peak temperature on such platforms, specially subject to hard real-time constraints. Therefore, we propose a study to effectively answer the pertinent research question: “How to offer users timing correctness and guarantees of hard real-time systems executed on heterogeneous multicore systems with energy and temperature constraints?”. Finding optimal solutions for such question has still several open research questions. The main aim of this thesis is to propose an energy optimization method for hard realtime system on heterogeneous multicore platform demonstrating that it is possible to timely compute timing correctness and guarantees using a sufficient and necessary condition; accounting for energy, temperature, preemption, precedence, shared resources constraints, and architectural interference. The proposal is a two fold approach. First, we investigate the process of finding the optimal task to core and frequency to task processes by means of applying exact schedulability tests for heterogeneous multicore platforms. Second, the outcome of the optimization analysis shall be used as reference to the on-line scheduler. We believe that we have achieved the main objective of this research by combining: (a) schedulability analysis from hard real-time systems, (b) representative mathematical formulations, based on integer linear programming, covering modern processors technological characteristics and using a classical combinatorial mathematical formulation (Multilevel Generalized Assignment Problem), and (c) robust exact implicit enumeration algorithmic strategies from combinatorial optimization, such as branch-and-cut and branch-and-price. The systematic literature review in the research subject reveals that the field has open questions to be answered. For instance, to the knowledge of the author only five works in the state-of-the-art literature deal with the problem by providing optimal solutions. Typically, the existing approaches focus on either heuristics or approximation algorithms. Also, only one work has a proposal to evaluate the schedulability in this scenario with an exact test. The typical formulation in the specialized literature is a 0/1 integer linear programming model which considers a continuous processor frequency domain and determines a single operating frequency per processor. One of the hypotheses tested in this research is: stronger feasibility analysis offers tighter bounds for the problem. We believe that this can be observed, for example, in the results produced by solvers for fixed priority schedulers, by means of an analysis based on a comparative study. By applying less accurate schedulability tests, such as utilization based, the solvers take longer to converge to optimal solutions, when compared to solvers that apply exact schedulability tests based on response time analysis. Another hypothesis tested in this research is: practical instances of the problem are timely solvable to optimal. We have experimented, by means of a comparative study, on finding feasible solutions for workload for fixed priority schedulers with up to 50 tasks distributed on four processors with seven different available frequencies. On independent hard real-time tasks scheduled using EDF policy, we found optimal distribution of up to 90 tasks on four processors with seven different available frequencies. In both cases, the solutions were found within 30 min of execution time. Similarly, on dependent tasks workload, we have optimally distributed 22 tasks, from an automotive control hard real-time application, on four processors with seven different available frequencies, with two shared resources and 23 precedence constraints within 1.5 h. We consider a few hours in the design phase a price worth paying in this context. / .

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