Reliability is of the utmost importance for safety of electronic systems built for the automotive, industrial, and medical sectors. In these systems, the embedded memory is especially sensitive due to the large number of minimum-sized devices in the cell arrays. Memory failures which occur after the manufacture-time burnin testing phase are particularly difficult to address since redundancy allocation is no longer available and fault detection schemes currently used in industry generally focus on the cell array while leaving the peripheral logic vulnerable to faults. Even in the cell array, conventional error control coding (ECC) has been limited in its ability to detect and correct failures greater than a few bits, due to the high latency or area overhead of correction [43]. Consequently, improvements to conventional memory resilience techniques are of great importance to continued reliable operation and to counter the raw bit error rate of the memory arrays in future technologies at economically feasible design points [11, 36, 37, 53, 56, 70]. In this thesis we examine the landscape of design techniques for reliability, and introduce two novel contributions for improving reliability with low overhead. To address failures occurring in the cell array, we have implemented an erasurebased ECC scheme (EB-ECC) that can extend conventional ECC already used in memory to correct and detect multiple erroneous bits with low overhead. An important component of this scheme is the method for detecting erasures at runtime; we propose a novel ternary-output sense amplifier design which can reduce the risk of undetected read latency failures in small-swing bitline designs. While most study has focused on the static random access memory (SRAM) cell array, for high-reliability products, it is important to examine the effects of failures on the peripheral logic as well. We have designed a wordline assertion comparator (WLAC) which has lower area overhead in large cache designs than competing techniques in the literature to detect address decoder failure.

The main contribution of this thesis is the statistical analysis of orthogonal frequency di- vision multiplexing (OFDM) systems operating over wireless channels that are both fre- quency selective and Rayleigh fading. We first describe the instantaneous capacity of such systems using a central limit theorem, as well as the asymptotic capacity of a power lim- ited OFDM system as the number of subcarriers approaches infinity. We then analyse the performance of uncoded OFDM systems by first developing bounds on the block error rate. Next we show that the distribution of the number of symbol errors within each block may be tightly approximated, and derive the distribution of an upper bound on the total variation distance. Finally, the central result of this thesis proposes the use of lattices for encodingOFDMsystems. For this, we detail a particular method of using lattices to encode OFDMsystems, and derive the optimalmaximumlikelihood decodingmetric. Generalised Minimum Distance (GMD) decoding is then introduced as a lower complexity method of decoding lattice encoded OFDM. We derive the optimal reliability metric for GMD decod- ing of OFDM systems operating over frequency selective channels, and develop analytical upper bounds on the error rate of lattice encoded OFDM systems employing GMD decod- ing.

No description available.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper presents a mathematical model for Coded Orthogonal Frequency Division Multiplexing (COFDM) in frequency selective multipath encountered in aeronautical telemetry. The use of the fast Fourier transform (FFT) for modulation and demodulation is reviewed. Error control coding with interleaving in frequency is able to provide reliable data communications during frequency selective multipath fade events. Simulations demonstrate QPSK mapped COFDM performs well in a multipath fading environment with parameters typically encountered in aeronautical telemetry.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / With the discovery of Turbo Codes in 1993, interest in developing error control coding schemes that approach channel capacity has intensified. Some of this interest has been focused on lowdensity parity-check (LDPC) codes due to their high performance characteristics and reasonable decoding complexity. A great deal of literature has focused on performance of regular and irregular LDPC codes of various rates and on a variety of channels. This paper presents the simulated performance results of a serial concatenated LDPC coding system on an AWGN channel. Performance and complexity comparisons between this serial LDPC system and typical LDPC systems are made.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / Three Quadrature Phase Shift Keying (QPSK) mapped COFDM systems demonstrating a continuum of complexity levels are simulated over an evolving three ray model of the multipath fading channel with parameters interpolated from actual channel sounding experiments. The first COFDM system uses coherent QPSK and convolutional coding with interleaving in frequency, channel equalization and soft decision decoding; the second uses convolutional coding with interleaving in frequency, Differential Phase Shift Keying (DPSK) and soft decision decoding; the third system uses a quaternary BCH code with DPSK mapping and Error and Erasure Decoding (EED). All three systems are shown to be able to provide reliable data communication during frequency selective fade events. Simulations demonstrate QPSK mapped COFDM with reasonable complexity performs well in a multipath frequency selective fading environment under parameters typically encountered in aeronautical telemetry.

In spread spectrum systems employing parity bit selected spreading sequences, parity bits generated from a linear block encoder are used to select a spreading code from a set of mutually orthogonal spreading sequences. In this thesis, turbo receivers for SS-PB systems are proposed and investigated. In the transmitter, data bits are rst convolutionally encoded before being fed into SS-PB modulator. In fact, the parity bit spreading code selection technique acts as an inner encoder in this system without allocating any transmit energy to the additional redundancy provided by this technique. The receiver implements a turbo processing by iteratively exchanging the soft information on coded bits between a SISO detector and a SISO decoder. In this system, detection is performed by incorporating the extrinsic information provided by the decoder in the last iteration into the received signal to calculate the likelihood of each detected bit in terms of LLR which is used as the input for a SISO decoder. In addition, SISO detectors are proposed for MC-CDMA and MIMO-CDMA systems that employ parity bit selected and permutation spreading. In the case of multiuser scenario, a turbo SISO multiuser detector is introduced for SS-PB systems for both synchronous and asynchronous channels. In such systems, MAI is estimated from the extrinsic information provided by the SISO channel decoder in the previous iteration. SISO multiuser detectors are also proposed for the case of multiple users in MC-CDMA and MIMO-CDMA systems when parity bit selected and permutation spreading are used. Simulations performed for all the proposed turbo receivers show a signi cant reduction in BER in AWGN and fading channels over multiple iterations.

In spread spectrum systems employing parity bit selected spreading sequences, parity bits generated from a linear block encoder are used to select a spreading code from a set of mutually orthogonal spreading sequences. In this thesis, turbo receivers for SS-PB systems are proposed and investigated. In the transmitter, data bits are rst convolutionally encoded before being fed into SS-PB modulator. In fact, the parity bit spreading code selection technique acts as an inner encoder in this system without allocating any transmit energy to the additional redundancy provided by this technique. The receiver implements a turbo processing by iteratively exchanging the soft information on coded bits between a SISO detector and a SISO decoder. In this system, detection is performed by incorporating the extrinsic information provided by the decoder in the last iteration into the received signal to calculate the likelihood of each detected bit in terms of LLR which is used as the input for a SISO decoder. In addition, SISO detectors are proposed for MC-CDMA and MIMO-CDMA systems that employ parity bit selected and permutation spreading. In the case of multiuser scenario, a turbo SISO multiuser detector is introduced for SS-PB systems for both synchronous and asynchronous channels. In such systems, MAI is estimated from the extrinsic information provided by the SISO channel decoder in the previous iteration. SISO multiuser detectors are also proposed for the case of multiple users in MC-CDMA and MIMO-CDMA systems when parity bit selected and permutation spreading are used. Simulations performed for all the proposed turbo receivers show a signi cant reduction in BER in AWGN and fading channels over multiple iterations.

In spread spectrum systems employing parity bit selected spreading sequences, parity bits generated from a linear block encoder are used to select a spreading code from a set of mutually orthogonal spreading sequences. In this thesis, turbo receivers for SS-PB systems are proposed and investigated. In the transmitter, data bits are rst convolutionally encoded before being fed into SS-PB modulator. In fact, the parity bit spreading code selection technique acts as an inner encoder in this system without allocating any transmit energy to the additional redundancy provided by this technique. The receiver implements a turbo processing by iteratively exchanging the soft information on coded bits between a SISO detector and a SISO decoder. In this system, detection is performed by incorporating the extrinsic information provided by the decoder in the last iteration into the received signal to calculate the likelihood of each detected bit in terms of LLR which is used as the input for a SISO decoder. In addition, SISO detectors are proposed for MC-CDMA and MIMO-CDMA systems that employ parity bit selected and permutation spreading. In the case of multiuser scenario, a turbo SISO multiuser detector is introduced for SS-PB systems for both synchronous and asynchronous channels. In such systems, MAI is estimated from the extrinsic information provided by the SISO channel decoder in the previous iteration. SISO multiuser detectors are also proposed for the case of multiple users in MC-CDMA and MIMO-CDMA systems when parity bit selected and permutation spreading are used. Simulations performed for all the proposed turbo receivers show a signi cant reduction in BER in AWGN and fading channels over multiple iterations.

abstract: Memory systems are becoming increasingly error-prone, and thus guaranteeing their reliability is a major challenge. In this dissertation, new techniques to improve the reliability of both 2D and 3D dynamic random access memory (DRAM) systems are presented. The proposed schemes have higher reliability than current systems but with lower power, better performance and lower hardware cost. First, a low overhead solution that improves the reliability of commodity DRAM systems with no change in the existing memory architecture is presented. Specifically, five erasure and error correction (E-ECC) schemes are proposed that provide at least Chipkill-Correct protection for x4 (Schemes 1, 2 and 3), x8 (Scheme 4) and x16 (Scheme 5) DRAM systems. All schemes have superior error correction performance due to the use of strong symbol-based codes. In addition, the use of erasure codes extends the lifetime of the 2D DRAM systems. Next, two error correction schemes are presented for 3D DRAM memory systems. The first scheme is a rate-adaptive, two-tiered error correction scheme (RATT-ECC) that provides strong reliability (10^10x) reduction in raw FIT rate) for an HBM-like 3D DRAM system that services CPU applications. The rate-adaptive feature of RATT-ECC enables permanent bank failures to be handled through sparing. It can also be used to significantly reduce the refresh power consumption without decreasing the reliability and timing performance. The second scheme is a two-tiered error correction scheme (Config-ECC) that supports different sized accesses in GPU applications with strong reliability. It addresses the mismatch between data access size and fixed sized ECC scheme by designing a product code based flexible scheme. Config-ECC is built around a core unit designed for 32B access with a simple extension to support 64B and 128B accesses. Compared to fixed 32B and 64B ECC schemes, Config-ECC reduces the failure in time (FIT) rate by 200x and 20x, respectively. It also reduces the memory energy by 17% (in the dynamic mode) and 21% (in the static mode) compared to a state-of-the-art fixed 64B ECC scheme. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017