This thesis presents the design, implementation, and fabrication of a pattern-guided equalizer in a 65nm CMOS process. By counting the occurrence of 6 out of 16 4-bit patterns in the received data and utilizing their spectral content, the signal is equalized separately at fN and fN/2, where fN is half the bit rate. The design was packaged using a 64 pin Quad Flat No leads (QFN) package. Two different channels were used and the equalizer was able to open the eye for both 13dB and 17dB of attenuation at the Nyquist frequency. The adaptation performance was determined by measuring the vertical and horizontal eye openings for all possible equalizer coefficients. Measured results at 6Gb/s confirm that the adaptation engine opens a closed eye to within 2.6% of optimal vertical opening and 7% of optimal horizontal eye opening while consuming 16.8mW from a 1.2V supply.

This thesis presents the design, implementation, and fabrication of a pattern-guided equalizer in a 65nm CMOS process. By counting the occurrence of 6 out of 16 4-bit patterns in the received data and utilizing their spectral content, the signal is equalized separately at fN and fN/2, where fN is half the bit rate. The design was packaged using a 64 pin Quad Flat No leads (QFN) package. Two different channels were used and the equalizer was able to open the eye for both 13dB and 17dB of attenuation at the Nyquist frequency. The adaptation performance was determined by measuring the vertical and horizontal eye openings for all possible equalizer coefficients. Measured results at 6Gb/s confirm that the adaptation engine opens a closed eye to within 2.6% of optimal vertical opening and 7% of optimal horizontal eye opening while consuming 16.8mW from a 1.2V supply.