Ulm, Univ., Diss., 2008.

MEMS microphones have been a research topic for the last two and half decades. The state-of-the-art comprises surface mount MEMS microphones in laptops, mobile phones and tablets, etc. The popularity and the commercial success of MEMS microphones is largely due to the steep cost reduction in manufacturing afforded by the mass scale production with microfabrication technology. The current MEMS microphones are de-signed along the lines of traditional microphones that use capacitive transduction with or without permanent charge (electret type microphones use permanent charge of their sensor element). These microphones offer high sensitivity, stability and reasonably at frequency response while reducing the overall size and energy consumption by exploiting MEMS technology. Conceptually, microphones are simple transducers that use a membrane or diaphragm as a mechanical structure which deflects elastically in response to the incident acoustic pressure. This dynamic deflection is converted into an electrical signal using an appropriate transduction technique. The most popular transduction technique used for this application is capacitive, where an elastic diaphragm forms one of the two parallel plates of a capacitor, the fixed substrate or the base plate being the other one. Thus, there are basically two main elements in a microphone { the elastic membrane as a mechanical element, and the transduction technique as the electrical element. In this thesis, we propose and study novel design for both these elements. In the mechanical element, we propose a simple topological change by introducing slits in the membrane along its periphery to enhance the mechanical sensitivity. This simple change, however, has significant impact on the microphone design, performance and its eventual cost. Introduction of slits in the membrane makes the geometry of the structural element non-trivial for response analysis. We devote considerable effort in devising appropriate modeling techniques for deriving lumped parameters that are then used for simulating the system response. For transduction, we propose and study an FET (Field Effect Transistor) coupled micro-phone design where the elastic diaphragm is used as the moving (suspended) gate of an FET and the gate deflection modulated drain current is used in the subthreshold regime of operation as the output signal of the microphone. This design is explored in detail with respect to various design parameters in order to enhance the electrical sensitivity. Both proposed changes in the microphone design are motivated by the possibilities that the microfabrication technology offers. In fact, the design proposed here requires further developments in MEMS technology for reliably creating gaps of 50-100 nm between the substrate and a large 2D structure of the order of a few hundred microns in diameter. In the First part of the thesis, we present detailed simulations of acoustic and squeeze lm domain to understand the effect slits could bring upon the behaviour of the device as a microphone. Since the geometry is nontrivial, we resort to Finite element simulations using commercial packages such as COMSOL Multiphysics and ANSYS in the structural, acoustic and Fluid-structure domains to analyze the behaviour of a microphone which has top plate with nontrivial geometry. On the simulated Finite element data, we conduct low and high frequency limit analysis to extract expressions for the lumped parameters. This technique is well known in acoustics. We borrow this technique of curve Fitting from the acoustics domain and apply it in modified form into the squeeze lm domain. The dynamic behaviour of the entire device is then simulated using the extracted parameters. This helps to simulate the microphone behaviour either as a receiver or as a transmitter. The designed device is fabricated using MEMSCAP PolyMUMPS process (a foundry Polysilicon surface micromachining process). We conduct vibrometer (electrostatic ex-citation) and acoustic characterization. We also study the feasibility of a microphone with slits and the issues involved. The effect of the two dissipation modes (acoustic and squeeze lm ) are quantified with the experimentally determined quality factor. The experimentally measured values are: Resonance is 488 kHz (experimentally determined), low frequency roll-off is 796 Hz (theoretical value) and is 780 Hz as obtained by electrical characterization. The first part of this thesis focusses on developing a comprehensive understanding of the effect of slits on the performance of a MEMS microphone. The presence of slits near the circumference of the clamped plate cause reduction in its rigidity. This leads to an increase in the sensitivity of the device. Slits also cause pressure equalization between the top and bottom of the diaphragm if the incoming sound is at relatively low frequencies. At this frequency, also known as the lower cutoff frequency, the microphone's response starts dropping. The presence of slits also changes the radiation impedance of the plate as well as the squeeze lm damping below the plate. The useful bandwidth of the microphone changes as a consequence. The cavity formed between the top plate and the bottom fixed substrate increases the stiffness of the device significantly due to compression of the trapped air. This effect is more pronounced here because unlike the existing capacitive MEMS microphones, there is no backchamber in the device fabricated here. In the second part of the thesis, we present a novel subthreshold biased FET based MEMS microphone. This biasing of the transistor in the subthreshold region (also called as the OFF-region) offers higher sensitivity as compared to the above threshold region (also called as the ON-region) biasing. This is due to the exponentially varying current with change in the bias voltage in the OFF-region as compared to the quadratic variation in the ON-region. Detailed simulations are done to predict the behaviour of the device. A lumped parameter model of the mechanical domain is coupled with the drain current equations to predict the device behaviour in response to the deflection of the moving gate. From the simulations, we predict that the proposed biasing offers a device sensitive to even sub-nanometer deflection of the flexible gate. As a proof of concept, we fabricate fixed-fixed beams which utilize CMOS-MEMS fabrication. The process involves six lithography steps which involve two CMOS and the remaining MEMS fabrication. The fabricated beams are mechanically characterized for resonance. Further, we carry out electrical characterization for I-V (current-voltage) characteristics. The second part of the thesis focusses on a novel biasing method which circumvents the need of signal conditioning circuitry needed in a capacitive based transduction due to inbuilt amplification. Extensive simulations with equivalent circuit has been carried out to determine the increased sensitivity and the role of various design variables.

MEMS Sensors are widely used for sensing inertial displacements. The displacements arising out of acceleration /Coriolis effect are typically in the range of 1 nm-1 m. This work investigates the realization of high resolution MEMS inertial sensors using novel displacement sensing mechanisms. Capacitance sensing ASIC is developed as part of conventional electronics interface with MEMS sensor under the conventional CMOS-MEMS integration strategy. The capacitance sense ASIC based on Continuous Time Voltage scheme with coherent and non-coherent demodulation is prototyped on AMS 0.35 m technology. The ASIC was tested to sense C = 3.125 fF over a base of 2 pF using on-chip built-in test capacitors. Dynamic performance of this ASIC was validated by interfacing with a DaCM MEMS accelerometer. 200milli-g of acceleration (equivalent to a C = 2.8 fF) over an input frequency of 20Hz is measurable using the developed ASIC. The observed sensitivity is 90mV/g. The ASIC has several programmable features such as variation in trim capacitance (3.125 fF-12.5 pF), bandwidth selection (500 Hz-20 kHz) and variable gain options (2-100). Capacitance detection, a dominant sensing principle in MEMs sensors, experiences inherent limitation due to the role of parasitics when the displacements of interest are below 5 nm range. The capacitive equivalence ( C) for the range of displacements of the order of 5 nm and below would vary in the range atto-to-zepto farad. Hence there is a need to explore alternative sensing schemes which preferably yield higher sensitivity (than those offered by the conventional integration schemes) and are based on the principle of built-in transduction to help overcome the influence of parasitics on sensitivity. In this regard, 3 non-conventional architectures are explored which fall under the direct integration classification namely: (a) Sub-threshold based sensing (b) Fringe field based sensing and (c) Tunneling current based sensing. a) In Sub-threshold based sensing, FET with a suspended gate is used for displacement sensing. The FET is biased in the sub-threshold region of operation. The exponential modulation of drain current for a change in displacement of 1 nm is evaluated using TCAD, and the in uence of initial air-gap variation on the sensitivity factor ( ID=ID) is brought out. For 1% change in air gap displacement (i.e., TGap/TGap, the gap variation resulting due to the inertial force / mass loading) nearly 1050% change in drain current( ID=ID) is observed (considering initial air gaps of the order 100 nm). This validates the high sensitivity offered by the device in this regime of operation. A comparison of sensitivity estimate using the capacitive equivalence model and TCAD simulated model for different initial air-gaps in a FD-SOI FET is brought out. The influence of FDSOI FET device parameters on sensitivity, namely the variation of TSi, TBox, NA and TGap are explored. CMOS compatibility and fabrication feasibility of this architecture was looked into by resorting to the post processing approach used for validating the sub-threshold bias concept. The IMD layers of the Bulk FETs fabricated through AMS 0.35 technology were etched using BHF and IPA mixture to result in a free standing metal (Al) layers acting as the suspended gate. The performance estimate is carried out considering specific Equivalent Gap Thickness (EGT) of 573 nm and 235 nm, to help overcome the role of coupled electrostatics in influencing the sensitivity metric. The sensitivity observed by biasing this post processed bulk FET in sub-threshold is 114% ( ID=ID change) for a 59% ( d/d change). The equivalent C in this case is 370 aF. b) In Fringe eld based sensing approach, a JunctionLess FET (JLFET) is used as a depletion mode device and an out-of-plane gate displacement would help modulate the device pinch-o voltage due to fringe field coupling. The resulting change in the gate fringe field due to this displacement modulates the drain current of the JunctionLess FET. The displacement induced fringe field change (relative to the FET channel) brings about a distinct shift in the ID-VG characteristics of the JLFET. For displacement d = 2 nm, the JLFET with a channel doping of ND = 8X1018cm 3 and a bias point of VG = -47.7 V, 98% enhancement in sensitivity is observed in 3D TCAD simulations. The equivalent C in this case is 29 zF. The role of ground-planes in the device operation is explored. c) In the tunneling current based sensing approach, the beams fabricated using the SOI-MUMPS process are FIB milled so as to create very ne air gaps of the order of nearly 85 nm. Under high electric fields of the order > 8 MV/cm, the lateral displacement based tunneling sensor offers enhanced change in sensitivity for an induced external force at a fixed DC bias. When integrated as an array with varying electrode overlap, this technique can track displacements over a wide range. With the initial beam overlap as 1.2 m, for a lateral displacement of 1.2 m, a 100% change in sensitivity ( ID=ID) is observed. The effect of fringe field can be completely neglected here unlike its capacitive beam equivalent.