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An FIFO Memory Design for Data Exchange Bus and Analog Front-end of Digital Cordless Headset Baseband ControllerChen, Yi-Wei 24 June 2002 (has links)
Three different chip design topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of an FIFO memory design for 8-to-32 data exchange bus. An FIFO memory architecture is proposed to be utilized in data exchange between processing units which possess non-homogeneous bus widths. Neither arbiter logics nor modules are required in such a design to determine input sequences or output sequences. Hence, the delay is drastically shortened.
The second topic is focused on the implementation of an analog front-end of digital cordless headset baseband controller. The integrated analog and digital interface IC provides an interface for analog and digital communication. It converts an analog signal into an 8-bit digital signal, which will be processed by the baseband controller. It also converts an 8-bit digital voice data into an analog voice signal. In addition, a built-in oscillator is included in the design, which provides a global clock signal.
The third topic is to carry out an DC/DC converter with a built-in voltage detector. The converter can convert 1.5V input voltage to 2.7V output voltage. A portable system can use only one single battery to power on by this circuit. It also contains a voltage detector to indicate whether the output voltage meets the pre-determined level.
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