No description available.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Electrical Engineering and Computer Engineering, 2006. / Includes bibliographical references (leaves 107-122).

Thesis (M.S.)--Worcester Polytechnic Institute. / Keywords: intrusion detection system; Byzantine Agreement Protocol. Includes bibliographical references (p. 43-44).

Thesis (M. Phil.)--University of Hong Kong, 1997. / Includes bibliographical references (leaves 111-112).

Thesis (Ph. D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2004. / "A dissertation in computer networking and telecommunication networking." Advisor: Deep Medhi. Typescript. Vita. Title from "catalog record" of the print edition Description based on contents viewed Feb. 24, 2006. Includes bibliographical references (leaves 140-147). Online version of the print edition.

Thesis (M.S. in electrical engineering)--Washington State University, August 2007. / Includes bibliographical references (p. 57-59).

No description available.

published_or_final_version / Physics / Doctoral / Doctor of Philosophy

As people are becoming increasingly dependent on computerized systems, the need for these systems to be dependable is also increasing. However, programming dependable systems is difficult, especially when parallelism is involved. This is due in part to the fact that very few high-level programming languages support both fault-tolerance and parallel programming. This dissertation addresses this problem by presenting FT-Linda, a high-level language for programming fault-tolerant parallel programs. FT-Linda is based on Linda, a language for programming parallel applications whose most notable feature is a distributed shared memory called tuple space. FT-Linda extends Linda by providing support to allow a program to tolerate failures in the underlying computing platform. The distinguishing features of FT-Linda are stable tuple spaces and atomic execution of multiple tuple space operations. The former is a type of stable storage in which tuple values are guaranteed to persist across failures, while the latter allows collections of tuple operations to be executed in an all-or-nothing fashion despite failures and concurrency. Example FT-Linda programs are given for both dependable systems and parallel applications. The design and implementation of FT-Linda are presented in detail. The key technique used is the replicated state machine approach to constructing fault-tolerant distributed programs. Here, tuple space is replicated to provide failure resilience, and the replicas are sent a message describing the atomic sequence of tuple space operations to perform. This strategy allows an efficient implementation in which only a single multicast message is needed for each atomic sequence of tuple space operations. An implementation of FT-Linda for a network of workstations is also described. FT-Linda is being implemented using Consul, a communication substrate that supports fault-tolerant distributed programming. Consul is built in turn with the x-kernel, an operating system kernel that provides support for composing network protocols. Each of the components of the implementation has been built and tested.

Approved for public release; distribution is unlimited / The harsh radiation environment of space, the propensity for SEUs to perturb the operations of a silicon based electronics, the rapid development of microprocessor capabilities and hence software applications, and the high cost (dollars and time) to develop and prove a system, require flexible, reliable, low cost, rapidly developed system solutions. Consequently, a reconfigurable Triple Modular Redundant (TMR) System-on-a-Chip (SOC) utilizing Field Programmable Gate Arrays (FPGAs) provides a viable solution for space based systems. The Configurable Fault Tolerant Processor (CFTP) is such a system, designed specifically for the purpose of testing and evaluating, on orbit, the reliability of instantiated TMR soft-core microprocessors, as well as the ability to reconfigure the system to support any onboard processor function. The CFTP maximizes the use of Commercial Off-The-Shelf (COTS) technology to investigate a low-cost, flexible alternative to processor hardware architecture, with a Total Ionizing Dose (TID) tolerant FPGA as the basis for a SOC. The flexibility of a configurable processor, based on FPGA technology, will enable on-orbit upgrades, reconfigurations, and modifications to the architecture in order to support dynamic mission requirements. The CFTP payload consists of a Printed Circuit Board (PCB) of 5.3 inches x 7.3 inches utilizing a slightly modified PC/104 bus interface. The initial FPGA configuration will be an instantiation of a TMR processor, with included Error Detection and Correction (EDAC) and memory controller circuitry. The PCB is designed with requisite supporting circuitry including a configuration controller FPGA, SDRAM, and Flash memory in order to allow the greatest variety of possible configurations. The CFTP is currently manifested as a Space Test Program (STP) experimental payload on the Naval Postgraduate School's NPSAT1 and the United States Naval Academy's MidSTAR-1 satellites. / Major, United States Marine Corps