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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
201

Design and Performance Evaluation of Service Discovery Protocols for Vehicular Networks

Abrougui, Kaouther 28 September 2011 (has links)
Intelligent Transportation Systems (ITS) are gaining momentum among researchers. ITS encompasses several technologies, including wireless communications, sensor networks, data and voice communication, real-time driving assistant systems, etc. These states of the art technologies are expected to pave the way for a plethora of vehicular network applications. In fact, recently we have witnessed a growing interest in Vehicular Networks from both the research community and industry. Several potential applications of Vehicular Networks are envisioned such as road safety and security, traffic monitoring and driving comfort, just to mention a few. It is critical that the existence of convenience or driving comfort services do not negatively affect the performance of safety services. In essence, the dissemination of safety services or the discovery of convenience applications requires the communication among service providers and service requesters through constrained bandwidth resources. Therefore, service discovery techniques for vehicular networks must efficiently use the available common resources. In this thesis, we focus on the design of bandwidth-efficient and scalable service discovery protocols for Vehicular Networks. Three types of service discovery architectures are introduced: infrastructure-less, infrastructure-based, and hybrid architectures. Our proposed algorithms are network layer based where service discovery messages are integrated into the routing messages for a lightweight discovery. Moreover, our protocols use the channel diversity for efficient service discovery. We describe our algorithms and discuss their implementation. Finally, we present the main results of the extensive set of simulation experiments that have been used in order to evaluate their performance.
202

On Error Detection and Recovery in Elliptic Curve Cryptosystems

Alkhoraidly, Abdulaziz Mohammad January 2011 (has links)
Fault analysis attacks represent a serious threat to a wide range of cryptosystems including those based on elliptic curves. With the variety and demonstrated practicality of these attacks, it is essential for cryptographic implementations to handle different types of errors properly and securely. In this work, we address some aspects of error detection and recovery in elliptic curve cryptosystems. In particular, we discuss the problem of wasteful computations performed between the occurrence of an error and its detection and propose solutions based on frequent validation to reduce that waste. We begin by presenting ways to select the validation frequency in order to minimize various performance criteria including the average and worst-case costs and the reliability threshold. We also provide solutions to reduce the sensitivity of the validation frequency to variations in the statistical error model and its parameters. Then, we present and discuss adaptive error recovery and illustrate its advantages in terms of low sensitivity to the error model and reduced variance of the resulting overhead especially in the presence of burst errors. Moreover, we use statistical inference to evaluate and fine-tune the selection of the adaptive policy. We also address the issue of validation testing cost and present a collection of coherency-based, cost-effective tests. We evaluate variations of these tests in terms of cost and error detection effectiveness and provide infective and reduced-cost, repeated-validation variants. Moreover, we use coherency-based tests to construct a combined-curve countermeasure that avoids the weaknesses of earlier related proposals and provides a flexible trade-off between cost and effectiveness.
203

Fault Tolerant Nanoscale Microprocessor Design on Semiconductor Nanowire Grids

Wang, Teng 01 February 2009 (has links)
As CMOS manufacturing technology approaches fundamental limits, researchers are looking for revolutionary technologies beyond the end of the CMOS roadmap. Recent progress on devices, nano-manufacturing, and assembling of nanoscale structures is driving researchers to explore possible new fabrics, circuits and architectures based on nanoscale devices. Several fabric architectures based on various nanoscale devices have been proposed for nanoscale computation. These show great advantages over conventional CMOS technology but focus on FPGA-style applications. There has been no work shown for nanoscale architectures tuned for a processor application. This dissertation proposes a novel nanowire-based 2-D fabric referred to as Nanoscale Application-Specific IC (NASIC). Compared with other nanoscale fabric architectures, NASIC designs can be optimized for higher density and performance in an application-specific way (similar to ASIC in this aspect) and used as a fabric for processors. We present the design of a wire-streaming processor (WISP-0), which exercises many NASIC circuit styles and optimizations. A major goal of NASIC, and for other nanoscale architectures, is to preserve the density advantage of underlying nanodevices. Topological, doping and interconnect constraints can severely impact the effective density that can be achieved at the system level. To handle these constraints, we propose a comprehensive set of optimizations at both circuit and logic levels. Evaluations show that with combined optimizations, WISP-0 is still 39X denser than the equivalent design in 18nm CMOS technology (expected in 2018 by ITRS). Another key challenge for nanoscale computing systems is dealing with the unreliable nanodevices. The defect rate of nanodevices is expected to be orders of magnitude higher than what we are accustomed to with conventional CMOS processing based on lithography. In this dissertation, we first investigate various sources of defects/faults in NASIC circuits and analyze their impacts. Then, a hierarchical, multi-layer solution is proposed to tolerate defects/faults. Simulation shows that the yield of WISP-0 is as high as 50% even if as many as 15% transistors are defective. Estimations of the speed, power consumption of NASIC designs are also presented.
204

Replica placement algorithms for efficient internet content delivery.

Xu, Shihong January 2009 (has links)
This thesis covers three main issues in content delivery with a focus on placement algorithms of replica servers and replica contents. In a content delivery system, the location of replicas is very important as perceived by a quotation: Closer is better. However, considering the costs incurred by replication, it is a challenge to deploy replicas in a cost-effective manner. The objective of our work is to optimally select the location of replicas which includes sites for replica server deployment, servers for replica contents hosting, and en-route caches for object caching. Our solutions for corresponding applications are presented in three parts of the work, which makes significant contributions for designing scalable, reliable, and efficient systems for Internet content delivery. In the first part, we define the Fault-Tolerant Facility Allocation (FTFA) problem for the placement of replica servers, which relaxes the well known Fault-Tolerant Facility Location (FTFL) problem by allowing an integer (instead of binary) number of facilities per site. We show that the problem is NP-hard even for the metric version, where connection costs satisfy the triangle inequality. We propose two efficient algorithms for the metric FTFA problem with approximation factors 1.81 and 1.61 respectively, where the second algorithm is also shown to be (1.11,1.78)- and (1,2)-approximation through the proposed inverse dual fitting technique. The first bi-factor approximation result is further used to achieve a 1.52-approximation algorithm and the second one a 4-approximation algorithm for the metric Fault-Tolerant k-Facility Allocation problem, where an upper bound of facility number (i. e. k) applies. In the second part, we formulate the problem of QoS-aware content replication for parallel access in terms of combined download speed maximization, where each client has a given degree of parallel connections determined by its QoS requirement. The problem is further converted into the metric FTFL problem and we propose an approximation algorithm which is implemented in a distributed and asynchronous manner of communication. We show theoretically that the cost of our solution is no more than 2F* + RC*, where F* and C* are two components of any optimal solution while R is the maximum number of parallel connections. Numerical experiments show that the cost of our solutions is comparable (within 4% error) to the optimal solutions. In the third part, we establish mathematical formulation for the en-route web caching problem in a multi-server network that takes into account all requests (to any server) passing through the intermediate nodes on a request/response path. The problem is to cache the requested object optimally on the path so that the total system gain is maximized. We consider the unconstrained case and two QoS-constrained cases respectively, using efficient dynamic programming based methods. Simulation experiments show that our methods either yield a steady performance improvement (in the unconstrained case) or provide required QoS guarantees. / http://proxy.library.adelaide.edu.au/login?url= http://library.adelaide.edu.au/cgi-bin/Pwebrecon.cgi?BBID=1461921 / Thesis (Ph.D.) - University of Adelaide, School of Computer Science, 2009
205

Statistical algorithms for circuit synthesis under process variation and high defect density

Singh, Ashish Kumar, January 1900 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.
206

Feasability assessment of a Kalman filter approach to fault detection and fault-tolerance in a highly unstable system : the RIT heart pump /

Gillespie, Erin. January 2009 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 2009. / Typescript. Includes bibliographical references (leaves
207

Design and flight testing actuator failure accommodation controllers on WVU YF-22 research UAVS

Gu, Yu, January 2004 (has links)
Thesis (Ph. D.)--West Virginia University, 2004. / Title from document title page. Document formatted into pages; contains xiv, 145 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 138-145).
208

Discrete event development framework for highly reliable sensor fusion systems /

Rokonuzzaman, Mohd., January 1999 (has links)
Thesis (Ph. D.), Memorial University of Newfoundland, 1999. / Bibliography: p. 131-137.
209

Formal specification of requirements for analytical redundancy based fault tolerant flight control systems

Del Gobbo, Diego. January 2000 (has links)
Thesis (Ph. D.)--West Virginia University, 2000. / Title from document title page. Document formatted into pages; contains ix, 185 p. : ill. Includes abstract. Includes bibliographical references (p. 87-91).
210

Estimating the dynamic sensitive cross section of an FPGA design through fault injection /

Johnson, Darrel E., January 2005 (has links) (PDF)
Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2005. / Includes bibliographical references (p. 105-108).

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