As people are becoming increasingly dependent on computerized systems, the need for these systems to be dependable is also increasing. However, programming dependable systems is difficult, especially when parallelism is involved. This is due in part to the fact that very few high-level programming languages support both fault-tolerance and parallel programming. This dissertation addresses this problem by presenting FT-Linda, a high-level language for programming fault-tolerant parallel programs. FT-Linda is based on Linda, a language for programming parallel applications whose most notable feature is a distributed shared memory called tuple space. FT-Linda extends Linda by providing support to allow a program to tolerate failures in the underlying computing platform. The distinguishing features of FT-Linda are stable tuple spaces and atomic execution of multiple tuple space operations. The former is a type of stable storage in which tuple values are guaranteed to persist across failures, while the latter allows collections of tuple operations to be executed in an all-or-nothing fashion despite failures and concurrency. Example FT-Linda programs are given for both dependable systems and parallel applications. The design and implementation of FT-Linda are presented in detail. The key technique used is the replicated state machine approach to constructing fault-tolerant distributed programs. Here, tuple space is replicated to provide failure resilience, and the replicas are sent a message describing the atomic sequence of tuple space operations to perform. This strategy allows an efficient implementation in which only a single multicast message is needed for each atomic sequence of tuple space operations. An implementation of FT-Linda for a network of workstations is also described. FT-Linda is being implemented using Consul, a communication substrate that supports fault-tolerant distributed programming. Consul is built in turn with the x-kernel, an operating system kernel that provides support for composing network protocols. Each of the components of the implementation has been built and tested.

Approved for public release; distribution is unlimited / The harsh radiation environment of space, the propensity for SEUs to perturb the operations of a silicon based electronics, the rapid development of microprocessor capabilities and hence software applications, and the high cost (dollars and time) to develop and prove a system, require flexible, reliable, low cost, rapidly developed system solutions. Consequently, a reconfigurable Triple Modular Redundant (TMR) System-on-a-Chip (SOC) utilizing Field Programmable Gate Arrays (FPGAs) provides a viable solution for space based systems. The Configurable Fault Tolerant Processor (CFTP) is such a system, designed specifically for the purpose of testing and evaluating, on orbit, the reliability of instantiated TMR soft-core microprocessors, as well as the ability to reconfigure the system to support any onboard processor function. The CFTP maximizes the use of Commercial Off-The-Shelf (COTS) technology to investigate a low-cost, flexible alternative to processor hardware architecture, with a Total Ionizing Dose (TID) tolerant FPGA as the basis for a SOC. The flexibility of a configurable processor, based on FPGA technology, will enable on-orbit upgrades, reconfigurations, and modifications to the architecture in order to support dynamic mission requirements. The CFTP payload consists of a Printed Circuit Board (PCB) of 5.3 inches x 7.3 inches utilizing a slightly modified PC/104 bus interface. The initial FPGA configuration will be an instantiation of a TMR processor, with included Error Detection and Correction (EDAC) and memory controller circuitry. The PCB is designed with requisite supporting circuitry including a configuration controller FPGA, SDRAM, and Flash memory in order to allow the greatest variety of possible configurations. The CFTP is currently manifested as a Space Test Program (STP) experimental payload on the Naval Postgraduate School's NPSAT1 and the United States Naval Academy's MidSTAR-1 satellites. / Major, United States Marine Corps

Wong, Tsz-Yeung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 77-79). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Related Work --- p.2 / Chapter 1.2 --- Progressive Fault-Tolerant Mechanism --- p.4 / Chapter 1.3 --- Organization of This Thesis --- p.7 / Chapter 1.4 --- Contribution of The Thesis --- p.8 / Chapter 2 --- Server Failure Detection and Recovery --- p.9 / Chapter 3 --- Agent Failure Detection and Recovery --- p.12 / Chapter 3.1 --- System Architecture --- p.12 / Chapter 3.2 --- Protocol Design --- p.14 / Chapter 3.3 --- Failure and Recovery Scenarios --- p.16 / Chapter 3.3.1 --- When fails to receive msgiarrive --- p.17 / Chapter 3.3.2 --- Whenwi-1 fails to receive msgieave --- p.19 / Chapter 3.3.3 --- Failures of the witness agents and recovery scenarios --- p.22 / Chapter 3.3.4 --- Catastrophic failures --- p.24 / Chapter 3.4 --- Simplification --- p.24 / Chapter 4 --- Fault-Tolerant Mechanism Analysis --- p.27 / Chapter 4.1 --- Definitions and Notations --- p.27 / Chapter 4.2 --- Assumptions --- p.29 / Chapter 4.3 --- The Algorithm --- p.30 / Chapter 4.3.1 --- Informal algorithm descriptions --- p.30 / Chapter 4.3.2 --- Formal algorithm descriptions --- p.32 / Chapter 4.4 --- Liveness Proof --- p.39 / Chapter 4.5 --- Simplification Analysis --- p.52 / Chapter 5 --- Link Failure Analysis --- p.61 / Chapter 5.1 --- Problems of Link Failure --- p.61 / Chapter 5.2 --- Solution --- p.62 / Chapter 6 --- Reliability Evaluation --- p.67 / Chapter 6.1 --- Server Failure Detection Analysis --- p.68 / Chapter 6.2 --- Agent Failure Detection Analysis --- p.71 / Bibliography --- p.77 / A Glossary --- p.80

Typescript (photocopy). / Digitized by Kansas Correctional Industries

The development of fault-tolerant computing systems is a very difficult task. Two reasons contributed to this difficulty can be described as follows. The First is that, in normal practice, fault-tolerant computing policies and mechanisms are deeply embedded into most application programs, so that these application programs cannot cope with changes in environments, policies and mechanisms. These factors may change frequently in a distributed environment, especially in a heterogeneous environment. Therefore, in order to develop better fault-tolerant systems that can cope with constant changes in environments and user requirements, it is essential to separate the fault tolerant computing policies and mechanisms in application programs. The second is, on the other hand, a number of techniques have been proposed for the construction of reliable and fault-tolerant computing systems. Many computer systems are being developed to tolerant various hardware and software failures. However, most of these systems are to be used in specific application areas, since it is extremely difficult to develop systems that can be used in general-purpose fault-tolerant computing. The motivation of this thesis is based on these two aspects. The focus of the thesis is on developing a model based on the reactive system concepts for building better fault-tolerant computing applications. The reactive system concepts are an attractive paradigm for system design, development and maintenance because it separates policies from mechanisms. The stress of the model is to provide flexible system architecture for the general-purpose fault-tolerant application development, and the model can be applied in many specific applications. With this reactive system model, we can separate fault-tolerant computing polices and mechanisms in the applications, so that the development and maintenance of fault-tolerant computing systems can be made easier.

Graduation date: 1994

Thesis (M.S.)--Rutgers University, 2009. / "Graduate Program in Electrical and Computer Engineering." Includes bibliographical references (p. 60-62).

Thesis (Ph. D.)--University of Hong Kong, 2009. / Includes bibliographical references (leaves 92-100). Also available in print.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 139-148). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 219-224). Also available online.