Spelling suggestions: "subject:"feedback control systems -- 1design"" "subject:"feedback control systems -- 22design""
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Reliable controller design for systems with transientsFeng, Lei 14 April 1998 (has links)
Reliable controller designs have been developed in this thesis for a number of finite-horizon
and infinite-horizon problems with possibly non-zero initial conditions. These
reliable controllers assure that system stability and system performance will be
maintained despite certain system faults. The performance measure used in this thesis is
an "H[subscript ���]-like norm", which is an induced two-norm from all exogenous signals and initial
conditions to the regulated output and final states. Controller designs and existence
conditions are presented for a reliable controller for faults in any pre-selected subset of
actuators or sensors. Also, controller designs and an existence condition are presented for
a reliable controller for any single sensor or actuator fault using sensor and actuator
redundancy. / Graduation date: 1999
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Adaptive output feedback controllers for a class of nonlinear mechanical systemsMiwa, Hideaki 28 August 2008 (has links)
Not available / text
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Recursive formulations of multibody systems in open loop configurationSarkar, Subhasis 08 1900 (has links)
No description available.
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Design of high-speed adaptive parallel multi-level decision feedback equalizerXiang, Yihai 26 February 1997 (has links)
Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision feedback equalization. Parallelism which doubles the symbol rate can be realized by setting the first tap of the feedback filter to zero.
A mixed-signal implementation has been chosen for the parallel MDFE, in which coefficients for the 9-tap feedback filter are adapted in the digital domain by 10-bit up/ down counters; 6-bit current mode D/A converters are used to convert digital coefficients to differential current signals which are summed with the forward equalizer (FE) output, and a flash A/D is used to make decisions and generate error signals for adaptation.
In this thesis, a description of the parallel structure and the adaptation algorithm are presented with behavioral level verification. The circuit design and layout were carried out in HP 1.2um n-well CMOS process. The design of the high-speed counter and the current-mode D/A are discussed. HSPICE simulations show that a symbol rate of 100Mb/s for the feedback equalizer is readily achieved. / Graduation date: 1997
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Design of high-speed low-power analog CMOS decision feedback equalizersSu, Wenjun 08 July 1996 (has links)
Decision feedback equalizer (DFE) is an effective method to remove inter-symbol
interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE
potentially offers higher speed, smaller die area, and lower power consumption when
compared to their digital counterparts.
Most of the available DFE equalizers were realized by using digital FIR filters
preceded by a flash A/D converter. Both the FIR filter and flash A/D converter are the
major contributers to the power dissipation. However, this project focuses on the analog
IC implementations of the DFE to achieve high speed and low power consumption. In
other words, this project gets intensively involved in the design of a large-input highly-linear
voltage-to-current converter, the design of a high-speed low-power 6-bit
comparator, and the design of a high-speed low-power 6-bit current-steering D/A
converter.
The design and layout for the proposed analog equalizer are carried out in a 1.2
pm n-well CMOS process. HSPICE simulations show that an analog DFE with 100 MHz
clock frequency and 6-bit accuracy can be easily achieved. The power consumption for
all the analog circuits is only about 24mW operating under a single 5V power supply. / Graduation date: 1997
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A probabilistic approach to aircraft design emphasizing stability and control uncertaintiesDeLaurentis, Daniel A. 12 1900 (has links)
No description available.
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Use of nonlinear elements for the control of a second order linear systemCullum, Clifton David 11 May 2010 (has links)
see document / Master of Science
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Human-Centered Design of an Air Quality Feedback System to Promote Healthy CookingIribagiza, Chantal 31 July 2018 (has links)
Household air pollution (HAP) is responsible for almost 4 million premature deaths every year, a burden that is primarily carried by women and children in developing countries. The mortality and morbidity impact of HAP can be significantly alleviated through clean cookstove interventions. However, for these interventions to be effective, the new intervention stove must be a substantially cleaner technology and adoption should be high and sustained over time.
Woody biomass is the fuel of choice in many developing communities, and contributes substantially to HAP. Several organizations have launched clean cooking interventions to address this issue. However, the majority of those interventions do not address adoption related challenges, that they often face.
This thesis explores previous studies on Human-Centered Design (HCD) and the impact of feedback and data access on behavior change. It details a HCD process and methodology applied during the design process of an air quality feedback system, to improve adoption of liquefied petroleum gas (LPG) cookstoves in Rwanda. The feedback system is intended to provide real-time air quality information to stove users and potentially encourage them to abandon traditional biomass cookstoves in favor of the cleaner LPG stoves.
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Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalizationGao, Hairong 23 June 1997 (has links)
Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm.
A mixed-signal IC implementation has been chosen for the parallel MDFE. The
differential current signals from the feedback equalizer are subtracted from the forward
equalizer output at the summing node to cancel the non-causal ISI. A high-speed
comparator with 6 bit resolution is used after the cancellation to detect the signal which
contains no ISI.
In this thesis, a description of the parallel MDFE structure and decision feedback
equalization algorithm are presented. The design of a high-speed summing circuitry and
a high-speed comparator are discussed. The same comparator design is used for the flash
analog-to-digital converter (ADC) which generates error signals for adaptation.The
circuits design and layout were carried out in an HP 1.2-��m n-well CMOS process. / Graduation date: 1998
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