Thesis (doctoral)--Helsinki University of Technology, 2009. / Includes bibliographical references. Also available on the World Wide Web.

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This work targeted the growth of gadolinium (Gd)-doped gallium nitride (GaN) thin films (Ga₁₋ₓGdₓN) by metal organic chemical vapor deposition (MOCVD). Characterization and evaluation of these Ga₁₋ₓGdₓN thin films for application in spintronics/optoelectronics devices also formed part of this work. This work presents: (1) the first report of stable, reproducible n- and p-type Ga₁₋ₓGdₓN thin films by MOCVD; (2) the first Ga₁₋ₓGdₓN p-n diode structure; and (3) the first report of a room temperature spin-polarized LED using a Ga₁₋ₓGdₓN spin injection layer. The Ga₁₋ₓGdₓN thin films grown in this work were electrically conductive, and co-doping them with Silicon (Si) or Magnesium (Mg) resulted in n-type and p-type materials, respectively. All the materials and structures grown in this work, including the Ga₁₋ₓGdₓN-based p-n diode and spin polarized LED, were characterized for their structural, optical, electrical and magnetic properties. The spin-polarized LED gave spin polarization ratio of 22% and systematic variation of this ratio at room temperature with external magnetic field was observed.

Thesis (M.S.)--University of Alabama at Birmingham, 2008. / Description based on contents viewed May 30, 2008; title from title screen. Includes bibliographical references (p. 50-51).

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This paper will describe the basics of ferroelectric devices for both hysteretic (non-volatile memory) and negative capacitance (steep slope switch) devices, and then project how these can be used in low-power logic cell architectures and fine-grain logic-in-memory (LiM) circuits.

So far, only CMOS compatible and scalable hafnia-zirconia (HZO) based ferroelectric (FE) n-FeFETs have been reported. To enable the full ferroelectric hierarchy [1] both p- and n-type devices should be available. Here we report a p-FeFET with a large memory window (MW) for the first time. Moreover, we propose different integration schemes comprising structures with and without internal gate resulting in metal-FE-insulator-Si (MFIS) and metal-FE-metal-insulator-Si (MFMIS) devices which could be used to tackle the problem of interface (IF) degradation and possibly decrease the power consumption of the devices.