Thesis (Ph. D.)--Ohio State University, 2005. / Available online via OhioLINK's ETD Center; full text release delayed at author's request until 2006 Jul 29.

Thesis (Ph. D.)--University of Washington, 2005. / Includes bibliographical references (leaves 129-132).

Thesis (M.S.)--Montana State University--Bozeman, 2006. / Typescript. Chairperson, Graduate Committee: Ross Snider. Includes bibliographical references (leaf 55).

Thesis (Ph. D.)--Drexel University, 2007. / Includes abstract and vita. Includes bibliographical references (leaves 114-121).

Thesis (Ph. D.)--Drexel University, 2007. / Includes abstract and vita. Includes bibliographical references (leaves 140-147).

Thesis (M.S.)--Rochester Institute of Technology, 2007. / Typescript. Includes bibliographical references (leaves 86-88).

Thesis (M.S. in Electrical Engineering)--Vanderbilt University, Aug. 2007. / Title from title screen. Includes bibliographical references.

Thesis (M.S.)--Baylor University, 2006. / Includes bibliographical references (p. 48).

Thesis (M.S.)--University of Texas at Dallas, 2008. / Includes vita. Includes bibliographical references (leaves 74-75)

Reductions in the cost and size of integrated circuits are allowing more and more complex functions to be included in previously simple tools such as lawn-mowers, ovens, and thermostats. Because of this, the process of synthesizing such functions from their initial representation to an optimal VLSI implementation is rarely hand-performed; instead, automated synthesis and optimization tools are a necessity. The factors such tools must take into account are numerous, including area (size), power consumption, and timing factors, to name just a few. Existing tools have traditionally focused upon optimization of two-level representations. However, new technologies such as Field Programmable Gate Arrays (FPGAs) have generated additional interest in three-level representations and structures such as Kronecker Decision Diagrams (KDDs). The reason for this is that when implementing a circuit on an FPGA, the cost of implementing exclusive-or logic is no more than that of traditional AND or OR gates. This dissertation investigates the use of the autocorrelation coefficients in logic synthesis for these types of structures; specifically, whether it is possible to pre-process a function to produce a subset of its autocorrelation coefficients and make use of this information in the choice of a three-level decomposition or of decomposition types within a KDD. This research began as a general investigation into the properties of autocorrelation coefficients of switching functions. Much work has centered around the use of a function's spectral coefficients in logic synthesis; however, very little work has used a function's autocorrelation coefficients. Their use has been investigated in the areas of testing, optimization for Programmable Logic Arrays (PLAs), identification of types of complexity measures, and in various DD-related applications, but in a limited manner. This has likely been due to the complexity in their computation. In order to investigate the uses of these coefficients, a fast computation technique was required, as well as knowledge of their basic properties. Both areas are detailed as part of this work, which demonstrates that it is feasible to quickly compute the autocorrelation coefficients. With these investigations as a foundation we further apply the autocorrelation coefficients to the development of a classification technique. The autocorrelation classes are similar to the spectral classes, but provide significantly different information. The dissertation demonstrates that some of this information highlighted by the autocorrelation classes may allow for the identification of exclusive-or logic within the function or classes of functions. In relation to this, a major contribution of this work involves the design and implementation of algorithms based on these results. The first of these algorithms is used to identify three-level decompositions for functions, and the second to determine decomposition type lists for KDD-representations. Each of these implementations compares well with existing tools, requiring on average less than one second to complete, and performing as well as the existing tools about 70% of the time. / Graduate