In this thesis, we propose a circuit design technique that reduces the energy utilized by any logic circuit for computation. We achieve this, by reducing the voltage swing on the circuit without greatly compromising the speed of operation and keeping in mind the noise margin constraints. Our technique involves the use of head or tail transistors that provide a Vth drop in the voltage swing. We choose to use head or tail transistors on alternate logic levels providing us with an option of driver stage, based on the noise margin of the subsequent stage. We demonstrate the working of this concept on inverter chains, to prove the correctness as well as the ability of the reduced voltage swing circuits to drive subsequent stages. We also discuss the implementation of this technique on basic gates and simple combinational circuits. We then show detailed experiments on a larger circuit, in this case a Kogge-Stone parallel prefix adder. We will discuss the overheads involved in the design and methods to partially overcome these by the use of selectively skewed gates and application of forward body bias. Finally we implement the same design using a different technology to demonstrate the scalability of the technique. / text