here is an increasing demand for higher bandwidth (BW) between logic and memory ICs for future smart mobile systems. Such high BW are proposed to be achieved using 3D interposers that have ultra-small through-package-via (TPVs) interconnections to connect the logic device on one side of the interposer to the memory on the other side. The current approach is primarily based on organic or silicon interposers. However, organic interposers face several challenges due to their poor dimensional stability, and coefficient of thermal expansion (CTE) mismatch to silicon ICs. Silicon interposers made with back-end-of-line (BEOL) wafer processes can achieve the required wiring and I/O density, but are not cost effective, and in addition exhibit higher electrical loss due to the semiconducting nature of the Si substrate. In this research, ultra-thin 3D Glass Interposers are studied as a superior alternative to organic and silicon interposers. The fundamental focus of this research is to achieve ultra-small TPVs in thin glass with dimensions similar to that of through-silicon-vias (TSVs) in silicon. The objective of this research is to study and demonstrate ultra-small pitch (30µm) TPV hole formation (10µm diameter), metallization and electrical characterization in ultra-thin (30µm) glass substrates. To meet these objectives, this study focusses on four main research tasks: a) electrical modeling and design of ultra-small TPVs in glass, b) small diameter TPV hole formation with minimum defects, c) copper metallization of TPVs with reliable adhesion, and d) electrical characterization of TPVs. This research reports the first demonstration of ultra-small TPVs (10-15µm in diameter) in ultra-thin glass interposer substrates (30µm). A thin-glass handling method is developed using polymer surface layers to achieve defect-free handling of glass even at thicknesses as low as 30µm. Several TPV formation methods are explored including excimer laser ablation using 193nm (ArF) lasers to form TPVs with smallest diameter and pitch. A brief study on the through-put capabilities of these excimer lasers is also discussed. The fundamental approach to TPV metallization involves a semi-additive-plating process (SAP) using electroless and electrolytic copper deposition techniques. The resulting side-wall surfaces of TPVs after metallization are analyzed through SEM imaging of TPV cross-sections, and are further characterized using nano-indentation tests. Additionally, thermo-mechanical reliability tests and failure analysis are performed to study the reliability of TPVs that are metallized with Cu. This research culminates in design, fabrication and electrical characterization of small pitch TPVs in ultra-thin glass interposers (30µm).

As the microelectronic industry moves toward stacking of dies to achieve greater performance and smaller footprint, there are several reliability concerns when assembling the stacked dies on current organic substrates. These concerns include excessive warpage, interconnect cracking, die cracking, and others. Silicon interposers are being developed to assemble the stacked dies, and then the silicon interposers are assembled on organic substrates. Although such an approach could address stacked-die to interposer reliability concerns, there are still reliability concerns between the silicon interposer and the organic substrate. This work examines the use of diced glass panel as an interposer, as glass provides intermediate coefficient of thermal expansion between silicon and organics, good mechanical rigidity, large-area panel processing for low cost, planarity, and better electrical properties. However, glass is brittle and low in thermal conductivity, and there is very little work in existing literature to examine glass as a potential interposer material. Starting with a 150 x 150 mm glass panel with a thickness of 100 µm, this work has built alternating layers of dielectric and copper on both sides of the panel. The panels have gone through typical cleanroom processes such as lithography, electroplating, etc. Upon fabrication, the panels are diced into individual substrates of 25 x 25 mm and a 10 x 10 mm flip chip with a solder bump pitch of 75 um is then reflow attached to the glass substrate followed by underfill dispensing and curing. The warpage of the flip-chip assembly is measured. In parallel to the experiments, numerical models have been developed. These models account for viscoplastic behavior of the solder. The models also mimic material addition and etching through element “birth-and-death” approach. The warpage from the models has been compared against experimental measurements for glass substrates with flip chip assembly. It is seen that the glass substrates provide significantly lower warpage compared to organic substrates, and thus could be a potential candidate for future 3D systems.

This paper demonstrates an approach for passive alignment and assembly of link components for board-level very-short range optical interconnects. This interchip optical link is based on planar polymeric multimode waveguides and glassbased electro-optical transceivers. The main aim of the work is the investigation of assembly processes of link components in order to fulfill the tolerance requirements using passive alignment. The optical characterization in regard to the optical coupling between link components will define the tolerances for the alignment process. This optical analysis is based on measurements of spatial coupling characteristics. The influence of assembly tolerances on the coupling efficiency is investigated. Flip-chip assembly of electro-optical devices on the glass interposer and of the glass interposer on optical overlay is presented to prove the implementation of the concept.

This paper discusses the technology development for integration of parallel optical interconnects on board-level, including the active and passive optical components as well as the electrical integrated circuitry. The inter-chip link is based on planar polymeric optical multimode waveguides with integrated out-of-plane coupling optics and optical transceiver subassemblies based on glass interposer. Integration of polymeric waveguides on flexible substrates will be shown since the realization of an overlay optical substrate enhances the yield and testability of the final hybrid electrooptical printed circuit board (EOPCB). Realized on-board waveguides feature low insertion loss (minimum attenuation coefficient of below 0.1 dB/cm). For short planar waveguides (Lwaveguide = 9 cm) error free transmission (BER < 10-12) up to 30 Gbit/s was achieved. The development of glass interposer passive optical coupling structures for VCSEL-based short-distance links will be described.