Verification of the on-die power grid is a key step in the design of complex high performance integrated circuits. For the very large grids in modern designs, incremental verification is highly desirable, because it allows one to skip the verification of a certain section of the grid (internal nodes) and instead, verify only the rest of the grid (external nodes). The focus of this work is to develop efficient techniques for incremental verification in the context of vectorless constraints-based grid verification, under dynamic conditions. The traditional difficulty is that the dynamic case requires iterative analysis of both the internal and the external sections. A solution in the transient case is provided through two key contributions: 1) a bound on the internal nodes’ voltages is developed that eliminates the need for iterative analysis, and 2) a multi-port Norton approach is used to construct a reduced macromodel for the internal section.

Verification of the on-die power grid is a key step in the design of complex high performance integrated circuits. For the very large grids in modern designs, incremental verification is highly desirable, because it allows one to skip the verification of a certain section of the grid (internal nodes) and instead, verify only the rest of the grid (external nodes). The focus of this work is to develop efficient techniques for incremental verification in the context of vectorless constraints-based grid verification, under dynamic conditions. The traditional difficulty is that the dynamic case requires iterative analysis of both the internal and the external sections. A solution in the transient case is provided through two key contributions: 1) a bound on the internal nodes’ voltages is developed that eliminates the need for iterative analysis, and 2) a multi-port Norton approach is used to construct a reduced macromodel for the internal section.

Zugl.: Karlsruhe, University, Diss., 2007.

Thesis (M.S.)--Naval Postgraduate School, 2004. / Title from title screen (viewed Mar. 15, 2005). "September 2004." "ADA427180"--URL. Includes bibliographical references (p. 89-90). Also issued in paper format.

Thesis (Ph. D.)--University of Hong Kong, 2000. / Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 1998. / Vita. Includes bibliographical references (leaves 238-250). Available also in a digital version from Dissertation Abstracts.

Zugl.: Potsdam, Univ., Diss., 2009

Techn. Univ., Diss., 2010--München.

Bayreuth, Univ., Diss., 2009.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Computer grids emerged in the 90 s with the goal of using geographically dispersed computers for high performance computing. Through grids, computational power of a supercomputer can be reached in a simple, efficient and inexpensive way. Such benefits led to highlights in researchs of computer grids. Recently, appeared on market graphics adapter cards whose computational power overcomes, and by a wide margin, even the most modern processors commonly used. This led to researchs that resulted in programming techniques relatively easy to learn and did simplify application programming for these processors. These techniques effectively introduced the processors in the business of high performance computing. The use of these techniques gave rise to General Purpose computing on Graphic Processing Units (GPGPU). Grids applications are generally programmed through a grid computing framework. TUXUR is one of those frameworks and is under development by Master s Program Graduate at the Federal University of Santa Maria. This dissertation discusses the development of a TUXUR s foreseen feature. Such feature allows the computer grid managed by TUXUR to enjoy the benefits of GPGPU applications, particularly regarding to the best use of the nodes s hardware that comprises it. The immediate impact of this synergy is the significant increase in grid computational capacity without adding new computers. The findings of the evaluation highlights the importance of using GPGPU tasks that take advantage of this programming technique, even when performed in a grid. / Grades de computadores surgiram na década de 90 com o objetivo de utilizar computadores geograficamente dispersos para computação de alto desempenho. Através destas grades, pode-se chegar ao poder computacional de um supercomputador de uma forma simples, eficiente e barata. Tais benefícios fizeram com que pesquisas em grades de computadores obtivessem destaques no ramo da computação. Recentemente, surgiram no mercado placas adaptadoras gráficas cujo poder computacional supera, e com larga vantagem, mesmo os mais modernos processadores de uso geral. Isso deu origem a pesquisas que resultaram em técnicas de programação relativamente fáceis de aprender e que simplificam a programação de aplicações para estes processadores. Estas técnicas efetivamente introduziram estes processadores no ramo de computação de alto desempenho. A utilização destas técnicas deu origem à programação de propósito geral em unidades de processamento gráfico (General-Purpose computation on Graphical Processor Units-GPGPU). Aplicações de grades são geralmente programadas através de um framework de computação em grade. TUXUR é um destes frameworks e encontra-se em desenvolvimento por mestrandos do Programa de Pós-graduação em Informática da Universidade Federal de Santa Maria. Este trabalho aborda o desenvolvimento de uma funcionalidade prevista no TUXUR. Tal funcionalidade permite que a grade de computadores gerenciada por TUXUR usufrua dos benefícios de aplicações GPGPU, sobretudo no que diz respeito à melhor utilização do hardware dos nós que a compõem. O reflexo imediato desta sinergia é o aumento significativo da capacidade computacional da grade sem o acréscimo de novos computadores. Os resultados encontrados na avaliação evidenciam a importância do uso de GPGPU nas tarefas que se beneficiam desta técnica de programação, mesmo quando executadas em uma grade.