CMOS is well known for its ability to scale. This fact is reflected in the aggressive scaling on a continual basis from the invention of CMOS up to date. As devices are scaled, device performance improves due to shorter channel lengths and more densely packed functions for the same amount of area. In recent years, however, the performance gain obtained through scaling has begun to suffer under the degradation of the associate interconnect performance. As devices become smaller, interconnects need to follow. Unlike transistors, the scaling of interconnects results in higher capacitances and resistances, thereby limiting overall system performance. Trying to alleviate the delay effects results in increased power consumption, especially in global structures such as clock distribution networks. A possible solution to this problem is the use of optical interconnects, which are fast and much less lossy than the electrical equivalents. This dissertation describes an investigation on what future technology nodes will entail in terms of power consumption of clock networks, and what is required for an optical alternative to become feasible. A common clock configuration is used as a basis for comparison, where both electrical and optical networks are designed to component level. Optimisation is done on both to ensure a reasonable comparison, and the results of the respective power consumption components are then compared in order to find the criteria for a feasible optical clock distribution scheme. Copyright / Dissertation (MEng)--University of Pretoria, 2009. / Electrical, Electronic and Computer Engineering / unrestricted

The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew.