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A dissertation submitted to the Faculty of Science, University of the Witwatersrand, Johannesburg, in fulfilment of requirements for the degree of Master of Science. Johannesburg, 2016. / The l1-norm solution to an under-determined system of linear equations y = Ax is the sparsest solution to the system. In digital signal processing this mathematical problem is known as compressive sensing. Compressive sensing provides a mathematical framework for sampling and reconstructing an analogue signal at a rate far lower than the rate provided by the standard information theory. The reconstruction from few samples is possible using non-linear optimization algorithms provided that the signal is sparse and the sensing matrix in incoherent. The major algorithmic challenge in compressive sensing is to efficiently and effectively find sparse solutions from minimal measurements. General purpose optimization algorithms are not suitable for solving non-differentiable l1-minimization problem. In this dissertation, we survey the major practical algorithms for nding l1-norm solution of under-determined linear system of equations. Specific attention is paid to computational issues, in which individual methods tends to perform well. We propose a hybrid algorithm that combines complementary strengths of the fixed-point method and the interior-point method. The strong feature of the xed-point method is its speed, while the strength of the interior-point method is accuracy. The hybrid algorithm combine the two methods in a probabilistic manner. The algorithm tends to prioritise a method that is efficient and robust. The computational performance of the hybrid algorithm is tested on simple signal reconstruction problems. The hybrid algorithm is shown to produce similar recoverability of sparse solution as that of the xed-point method and the interior-point method. Furthermore the proposed hybrid algorithm is comparative in terms of speed and accuracy with existing methods. / LG2017

Thesis--M. Phil., University of Hong Kong, 1980.

published_or_final_version / abstract / Electrical Engineering / Master / Master of Philosophy

Thesis (Ph.D.)--University of Central Florida, 2008. / Adviser: Luis Rabelo. Includes bibliographical references (p. 358-369).

An eight-node isoparametric hybrid stress element is developed for two dimensional plane stress and plane strain analyses. The assumed stresses are represented by 18 unknown parameters. An eight-node isoparametric displacement element is implemented in an existing finite element program [10]. Several example problems are solved to compare the results of the hybrid and the displacement elements. / Master of Science

by H.-N. Tan and S.B. Gershwin. / Bibliography: leaves 13-15. / "February, 1979." Caption title. / Supported by the U.S. Dept. of Transportation under Contract DOT-TSC-1456

Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1979 / Includes bibliographical references. / by Han-Ngee Tan. / M.S. / M.S. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

A methodology for representing and analyzing manufacturing systems in a hybrid systems framework for control reconfiguration purposes in the presence of defects and failures at the product and system levels is presented. At the top level, a supervisory Petri net directs parts/jobs through the manufacturing system. An object-based hybrid systems model that incorporates both Petri nets at the event-driven level and differential equations at the time-driven level describes the subsystems. Rerouting capabilities utilizing this model at the product and operation levels were explained. Simulations were performed on a testbed model for optimal time and mode transition cost to determine the route for parts. The product level reconfiguration architecture utilizes an adaptive network-based fuzzy inference system (ANFIS) to map histogram comparison metrics to set-point adjustments when product defects were detected. Tests were performed on good and defective plastic parts from a plastic injection molding machine. In addition, a mode identification architecture was described that incorporates both time- and event-driven information to determine the operating mode of a system from measured sensor signals. Simulated data representing the measured process signals from a Navy ship chiller system were used to verify that the appropriate operating modes were detected.

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in the applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). Computer architectures based on the dynamic dataflow model of computation have to be an infinite resource implementation to be able to exploit all available parallelism in all applications. It is not feasible for any real architectural implementation. When limited resource implementations are considered, there is a possibility of loss of performance (inability to efficiently exploit available parallelism). In this thesis, we study the throttling of execution in the REDEFINE architecture to maximize the architecture efficiency. We have formulated it as a design space exploration problem at two levels i.e. architectural configurations and throttling schemes. Reduced feature/high level simulation or feature specific analytical approaches are very useful for the selective study/exploration of early in design phase architectures/systems. Our approach is similar to that of SEASAME Framework which is used for the study of MPSoC (Multiprocessor SoC) architectures. We have used abstraction (feature reduction) at the levels of architecture and model of computation to make the problem approachable and practically feasible. A feature specific fast hybrid (mixed level) simulation framework for the early in design phase study is developed and implemented for the huge design space exploration (1284 throttling schemes, 128 architectural configurations and 10 applications i.e. 1.6 million executions). We have done performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigation of the effectiveness of the design space exploration using statistical hypothesis testing. We found some interesting obvious/intuitive and some non-obvious/counterintuitive results. The two performance criteria namely Exec.T and Avg.TU were found sufficient to represent the performance and the resource usage characteristics of the architecture independent of the throttling schemes, the architectural configurations and the applications. The ranking of the throttling schemes based on the selected performance criteria is found to be statistically very significant. The intuitive throttling schemes span the range of performance from the best to the worst. We found absence of trade-off amongst all of the performance criteria. The best throttling schemes give appreciable overall performance (25%) and resource usage (37%) gains in the throttling unit simultaneously. The design space exploration of the throttling schemes is found to be fine and uniform.