3D-NoC architectures are the amalgamation of the 3D integration (Die stacking of 3D-IC Technology) with the increased scalability found in NoC. Originally, it was proposed to tackle the problem of increasing the number of cores in the 2D plane which seems incompetent due to long distance interconnects. This architecture is aimed to optimize performance, power consumption, achieve low latency and increase the network bandwidth. Nevertheless, as more dies were being stacked vertically, IC operating frequency increases and this leads to some thermal issues which include high power density which increases average temperature. In addition to that, longer heat dissipation path results in different heat dissipation in each layer of the NoC which worsen the situation. An increase in the overall power consumption increases the average temperature, reduces performance and reliability. In this paper, an adaptive thermal-aware management scheme was proposed for 3D-NoCs, concentrating more on the hotspot regions in the network. This proposed protocol employs the thermal state of intermediate nodes and flits properties in a random uniform distributive way for packet routing. The proposed algorithm increases network availability and tends to distribute the temperature of the system evenly and uniformly within the network and making sure that packets are not forwarded to the hotspot node(s) and only flits with certain properties in the distribution are forwarded to the hotspot node(s). Before or during transmission, these two distributions must be calculated alongside the current node temperature to knowing which state of the distribution that node and flit belong to. The simulation shows this gave better performance in throughput and reliability of the network by reducing the number of hotspot nodes in the NoC. The proposed algorithm also reduces power consumption which is a function of temperature. Simulations show that our proposed algorithm reduces the total power/energy consumed by more than 59\% and throughput is improved by 69\% compared to a traditional XYZ routing. / Graduate

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / Increasing gate counts in FPGA’s create an option of offering multiple waveform demodulation and modulation within a single transponder transceiver. Differing data rates, channel schemes, and network protocols can be addressed with the flexibility of software-based demodulation and modulation. Increased satellite longevity and reliability are benefits of software-based transceiver design. Newer packaging technology offers additional capability in reducing form factor and weight of a transponder. A review of the challenges in combining each of the above to produce the next generation of transponders is the subject of this paper.